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IP101G-DS-R01 数据表(PDF) 27 Page - List of Unclassifed Manufacturers

部件名 IP101G-DS-R01
功能描述  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

IP101G-DS-R01 数据表(HTML) 27 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
27/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01
MII page16 register17
page
MII
ROM R/W
Description
Default
17[1]
RO
(SC)
Duplex Change
Flag to indicate duplex change interrupt
0
17[0]
RO
(SC)
Link Change
Flag to indicate link status change interrupt
0
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.
MII page16 register18
page
MII
ROM R/W
Description
Default
UTP PHY Interrupt Control/Status Register
18[15]
RO Reserved
0
18[14]
RO Resolved Speed
The resolved speed selection after auto negotiation or forced
mode
0
18[13]
RO Resolved Duplex
The resolved duplex selection after auto negotiation or forced
mode
0
18[12]
RO Reserved
0
18[11]
RO Resolved Auto negotiation completed
To indicate if auto negotiation is finished
0
18[10]
RO LINK_UP
To indicate the link status is OK or FAIL
0
18[9]
RO MDI/MDIX
To indicate which channel is selected by auto-MDIX.
1: MDIX is selected
0: MDI is selected
1
18[8]
RO POLARITY
To indicate the polarity of twist pair N/P is reversed
0
18[7]
RO JABBER
To indicate if jabber packet is received or not, when bit 16:<9>
is set high
0
18[6:4]
RO Reserved
0
16
18[3:0]
RO AN_ARBIT_STATE
To monitor the current value of N-WAY arbiter state machine
8: AUTO NEGOTIATION ENABLE
0: TRANSMIT DISABLE
1: ABILITY DETECT
5: ACKNOWLEDGE DETECT
4: COMPLETE ACKNOWLEDGE
12: NEXT PAGE WAIT
3: LINK STATUS CHECK
9: PARALLEL DETECTION FAULT
2: FLP LINK GOOD CHECK
10: FLP LINK GOOD
0x8
The other Registers are reserved registers. User is inhibited to access to these registers. It may
introduce abnormal function to write these registers.



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