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IP101G-DS-R01 数据表(PDF) 53 Page - List of Unclassifed Manufacturers

部件名 IP101G-DS-R01
功能描述  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

IP101G-DS-R01 数据表(HTML) 53 Page - List of Unclassifed Manufacturers

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IP101G
Data Sheet
Set low to RESET_N pin, for at least 10ms will reset all functions available in IP101G. The bit 15 of
Register 0 will put PHY into its default status.
5.9 Serial Management Interface
IP101G supports one serial management interface (SMI). User can access IP101G’s MII registers
through MDC and MDIO. Its format is shown in the following table. To access MII register in IP101G,
MDC should be at least one more cycle than MDIO. That is, a complete command consists of 32 bits
MDIO data and at least 33 MDC clocks. When the SMI is idle, MDIO is in high impedance.
Table 9 SMI Format
Frame
format
<Idle><start><op code><PHY address><Registers address><turnaround><data><idle>
Read
Operation
<Idle><01><10><A4A3A2A1A0><R4R3R2R1R0><Z0><b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
Write
Operation
<Idle><01><01><A4A3A2A1A0><R4R3R2R1R0><10><b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1..1
idle
start
op
code
PHY address =
01h
Reg address =
00h
TA
Register data
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
idle
A
4
A
3
A
2
A
1
A
0
R
4
R
3
R
2
R
1
R
0
write
z
z
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
Z
0
0
0
0
0
1
0
0
0
0
0
1
1
0
idle
start
op
code
PHY address =
01h
Reg address =
00h
TA
Register data
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
idle
A
4
A
3
A
2
A
1
A
0
R
4
R
3
R
2
R
1
R
0
read
z
zz
MDC
MDIO
MDC
MDIO
1..1
1..1
1..1
Figure 16 MDC/MDIO Format
53/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01



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