TDA4VEN...Q1 datasheet(143/236 Pages) TI

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•

gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK

•

gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK

(2)

In GPMC_WAIT[j], j is equal to 0 or 1.

(3)

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-

Purpose Memory Controller (GPMC) section in the device TRM.

(4)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

For not_div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–

GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

For GPMC_FCLK_MUX:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

Table 6-66. GPMC and NOR Flash Switching Characteristics – Synchronous Mode

see Figure 6-47, Figure 6-48, Figure 6-49, Figure 6-50, and Figure 6-51

NO.

(2)

PARAMETER

DESCRIPTION

MODE(16)

MIN

MAX

MIN

MAX

UNIT

100MHz

133MHz

1 / tc(clk)

Period, output clock GPMC_CLK(15)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

10.00

7.52

tw(clkH)

Typical pulse duration, output clock

GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0.475P

- 0.3(14)

0.475P

- 0.3(14)

tw(clkL)

Typical pulse duration, output clock

GPMC_CLK low

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0.475P

- 0.3(14)

0.475P

- 0.3(14)

td(clkH-csnV)

Delay time, output clock GPMC_CLK

rising edge to output chip select

GPMC_CSn[i] transition(13)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

F - 2.2

(5)

F +

3.75

F - 2.2

(5)

F +

3.75

td(clkH-CSn[i]V)

Delay time, output clock GPMC_CLK

rising edge to output chip select

GPMC_CSn[i] invalid(13)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

E - 2.2

(4)

E +

3.18

E - 2.2

(4)

E + 4.5

td(aV-clk)

Delay time, output address

GPMC_A[27:1] valid to output clock

GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

B - 2.3

(2)

B + 4.5 B - 2.3

(2)

B + 4.5

td(clkH-aIV)

Delay time, output clock GPMC_CLK

rising edge to output address

GPMC_A[27:1] invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2.3

4.5

-2.3

4.5

td(be[x]nV-clk)

Delay time, output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n valid to output

clock GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

B - 2.3

(2)

B + 1.9 B - 2.3

(2)

B + 1.9

td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK

rising edge to output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n invalid(10)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

D -

2.3(3)

D + 1.9 D - 2.3

(3)

D + 1.9

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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