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TDA4VEN...Q1 数据表(PDF) 144 Page - Texas Instruments |
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TDA4VEN...Q1 数据表(HTML) 144 Page - Texas Instruments |
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144 / 236 page  Table 6-66. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued) see Figure 6-47, Figure 6-48, Figure 6-49, Figure 6-50, and Figure 6-51 NO. (2) PARAMETER DESCRIPTION MODE(16) MIN MAX MIN MAX UNIT 100MHz 133MHz F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(11) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 D - 2.3 (3) D + 1.9 D - 2.3 (3) D + 1.9 ns F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n invalid(12) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 D - 2.3 (3) D + 1.9 D - 2.3 (3) D + 1.9 ns F8 td(clkH-advn) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE transition div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay G - 2.3(6) G + 4.5 G - 2.3 (6) G + 4.5 ns F9 td(clkH-advnIV) Delay time, output clock GPMC_CLK rising edge to output address valid and address latch enable GPMC_ADVn_ALE invalid div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay D - 2.3 (3) D + 4.5 D - 2.3 (3) D + 4.5 ns F10 td(clkH-oen) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn transition div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay H - 2.3 (7) H + 3.5 H - 2.3 (7) H + 3.5 ns F11 td(clkH-oenIV) Delay time, output clock GPMC_CLK rising edge to output enable GPMC_OEn_REn invalid div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay H - 2.3 (7) H + 3.5 H - 2.3 (7) H + 3.5 ns F14 td(clkH-wen) Delay time, output clock GPMC_CLK rising edge to output write enable GPMC_WEn transition div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1; no extra_delay I - 2.3 (8) I + 4.5 I - 2.3 (8) I + 4.5 ns F15 td(clkH-do) Delay time, output clock GPMC_CLK rising edge to output data GPMC_AD[15:0] transition(10) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 J - 2.3 (9) J + 2.7 J - 2.3 (9) J + 2.7 ns F15 td(clkL-do) Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(11) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 J - 2.3 (9) J + 2.7 J - 2.3 (9) J + 2.7 ns F15 td(clkL-do). Delay time, GPMC_CLK falling edge to GPMC_AD[15:0] data bus transition(12) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 J - 2.3 (9) J + 2.7 J - 2.3 (9) J + 2.7 ns F17 td(clkH-be[x]n) Delay time, output clock GPMC_CLK rising edge to output lower byte enable and command latch enable GPMC_BE0n_CLE transition(10) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 J - 2.3 (9) J + 1.9 J - 2.3 (9) J + 1.9 ns F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(11) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 J - 2.3 (9) J + 1.9 J - 2.3 (9) J + 1.9 ns F17 td(clkL-be[x]n). Delay time, GPMC_CLK falling edge to GPMC_BE0n_CLE, GPMC_BE1n transition(12) div_by_1_mode; GPMC_FCLK_MUX; TIMEPARAGRANULARITY_X1 J - 2.3 (9) J + 1.9 J - 2.3 (9) J + 1.9 ns F18 tw(csnV) Pulse duration, output chip select GPMC_CSn[i](13) low Read A A ns Write A A ns F19 tw(be[x]nV) Pulse duration, output lower byte enable and command latch enable GPMC_BE0n_CLE, output upper byte enable GPMC_BE1n low Read C C ns Write C C ns TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 144 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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