TDA4VEN...Q1 datasheet(206/236 Pages) TI

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Table 6-121. OSPI0 Switching Characteristics – PHY DDR Mode

see Figure 6-103

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

tw(CLKL)

Pulse duration, OSPI0_CLK low

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0_CLK high

((0.475P(1)) - 0.3)

td(CSn-CLK)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

((0.475P(1)) -

(0.975M(2)R(4)))

((0.525P(1)) -

(1.025M(2)R(4)) + 7)

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

((0.475P(1)) +

(0.975N(3)R(4)) - 7)

((0.525P(1)) +

(1.025N(3)R(4)))

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

1.8V

-7.71

-1.56

3.3V

-7.71

-1.56

(1)

P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = reference clock cycle time in ns

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 6-103. OSPI0 Switching Characteristics – PHY DDR

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

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