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TDA4VEN...Q1 数据表(PDF) 211 Page - Texas Instruments

部件名 TDA4VEN...Q1
功能描述  TDA4VEN, TDA4AEN Jacinto™ Processors
PDF  236 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TDA4VEN...Q1 数据表(HTML) 211 Page - Texas Instruments

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6.9.5.21 Timers
For more details about features and additional description information on the device Timers, see the
corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 6-126. Timer Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
0.5
5
V/ns
OUTPUT CONDITIONS
CL
Output load capacitance
2
10
pF
Table 6-127. Timer Input Timing Requirements
see Figure 6-108
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
T1
tw(TINPH)
Pulse duration, high
CAPTURE
4P(1)+
2.5
ns
T2
tw(TINPL)
Pulse duration, low
CAPTURE
4P(1)+
2.5
ns
(1)
P = functional clock period in ns.
Table 6-128. Timer Output Switching Characteristics
see Figure 6-108
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
T3
tw(TOUTH)
Pulse duration, high
PWM
4P(1) -
2.5
ns
T4
tw(TOUTL)
Pulse duration, low
PWM
4P(1) -
2.5
ns
(1)
P = functional clock period in ns.
T1
T2
TIMER_IOx (inputs)
TIMER_01
T3
T4
TIMER_IOx (outputs)
Figure 6-108. Timer Timing Requirements and Switching Characteristics
For more information, see Timers section in Peripherals chapter in the device TRM.
www.ti.com
TDA4VEN-Q1, TDA4AEN-Q1
SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1



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