TDA4VEN...Q1 datasheet(220/236 Pages) TI

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8.2.3 USB VBUS Design Guidelines

The USB 3.1 specification allows the VBUS voltage to be as high as 5.5V for normal operation, and as high as

20V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to

be 30V.

The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in

the Figure 8-4), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these

external resistors should be equal to or less than 1%, and the leakage current of Zener diode at 5V should be

less than 100nA.

Device

USBn_VBUS

J7ES_USB_VBUS_01

VSS

16.5 kΩ

10 kΩ

3.48 kΩ

VBUS signal

(BZX84C6V8 or equivalent)

6.8V

Figure 8-4. USB VBUS Detect Voltage Divider / Clamp Circuit

The USB0_VBUS pin can be considered to be fail-safe because the external circuit in Figure 8-4 limits the input

current to the actual device pin in a case where VBUS is applied while the device is powered off.

8.2.4 System Power Supply Monitor Design Guidelines

The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically

a single pre-regulated power source for the entire system and can be connected to the VMON_VSYS pin via

and external resistor divider circuit. This system supply is monitored by comparing the external voltage divider

output voltage to an internal voltage reference, where a power fail event is triggered when the voltage applied

to VMON_VSYS drops below the internal reference voltage. The actual system power supply voltage trip point

is determined by the system designer when selecting component values used to implement the external resistor

voltage divider circuit.

When designing the resistor divider circuit the designer must understand various factors which contribute to

variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of

the VMON_VSYS input threshold which has a nominal value of 0.45V, with a variation of ±3%. Precision

1% resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider.

This minimizes variability contributed by resistor value tolerances. Input leakage current associated with

VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the

voltage divider output. The VMON_VSYS input leakage current can be in the range of 10nA to 2.5µA when

applying 0.45V.

Note

The resistor voltage divider shall be designed such that the output voltage never exceeds the

maximum value defined in the Recommended Operating Conditions section, during normal operating

conditions.

Figure 8-5 presents an example, where the system power supply is nominally 5V and the maximum trigger

threshold is 5V - 10%, or 4.5V.

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

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