TMP86FS49AIUG datasheet(188/296 Pages) TOSHIBA

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Page 172

14. Synchronous Serial Interface (SIO1)

14.3 Function

TMP86FS49AIUG

(2)

During the transmit/receive operation

When data is written to SIO1TDB, SIO1SR<TXF> is cleared to “0” and when a data is read from

SIO1RDB, SIO1SR<RXF> is cleared to “0”.

In internal clock operation, in case of the condition described below, the serial clock stops to “H”

level by an automatic-wait function when all of the bit set in the data has been transmitted.

• Next transmit data is not written to SIO1TDB after reading a received data from SIO1RDB.

• Received data is not read from SIO1RDB after writing a next transmit data to SIO1TDB.

• Neither SIO1TDB nor SIO1RDB is accessed after transmission.

The automatic wait function is released by writing the next transmit data to SIO1TDB after reading

the received data from SIO1RDB, or reading the received data from SIO1RDB after writing the next

data to SIO1TDB.

Then, transmit/receive operation is restarted after maximum 1 cycle of serial clock.

In external clock operation, reading the received data from SIO1RDB and writing the next data to

SIO1TDB must be finished before the shift operation of the next data begins.

If the transmit data is not written to SIO1TDB after SIO1SR<TXF> is set to “1”, transmit error

occurs immediately after shift operation is started. When the transmit error occurred,

SIO1SR<TXERR> is set to “1”.

If received data is not read out from SIO1RDB before next shift operation starts after setting

SIO1SR<RXF> to “1”, receive error occurs immediately after shift operation is finished. When the

receive error has occurred, SIO1SR<RXERR> is set to “1”.

(3)

Stopping the transmit/receive operation

There are two ways for stopping the transmit/receive operation.

• The way of clearing SIO1CR<SIOS>.

When SIO1CR<SIOS> is cleared to “0”, transmit/receive operation is stopped after all trans-

fer of the data is finished. When transmit/receive operation is finished, SIO1SR<SIOF> is

cleared to “0” and SO1 pin is kept in high level.

In external clock operation, SIO1CR<SIOS> must be cleared to “0” before SIO1SR<SEF> is

set to “1” by beginning next transfer.

• The way of setting SIO1CR<SIOINH>.

Transmit/receive operation is stopped immediately after SIO1CR<SIOINH> is set to “1”. In

this case, SIO1CR<SIOS>, SIO1SR register, SIO1RDB register and SIO1TDB register are

initialized.

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