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TMP86FS49AIUG 数据表(PDF) 190 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 190 Page - Toshiba Semiconductor |
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190 / 296 page  Page 174 14. Synchronous Serial Interface (SIO1) 14.3 Function TMP86FS49AIUG Figure 14-14 Example of External Clock and MSB Transmit/Receive Mode (4) Transmit/receive error processing Transmit/receive errors occur on the following situation. Corrective action is different, which errors occur transmits or receives. (a) Transmit errors Transmit errors occur on the following situation. • Shift operation starts before writing next transmit data to SIO1TDB in external clock op- eration. If transmit errors occur during transmit operation, SIO1SR<TXERR> is set to “1” im- mediately after starting shift operation. And INTSIO1 interrupt request is generated af- ter all of the 8-bit data has been received. If shift operation starts before writing data to SIO1TDB after SIO1CR<SIOS> is set to “1”, SIO1SR<TXERR> is set immediately after starting shift operation. And INTSIO1 interrupt request is generated after all of the 8-bit data has been received. SO1 pin is kept in high level when SIO1SR<TXERR> is set to “1”. When transmit error occurs, transmit operation must be forcibly stop by writing SIO1CR<SIOINH> to “1” after the received data is read from SIO1RDB. In this case, SIO1CR<SIOS>, SIO1SR register, SIO1RDB register and SIO1TDB register are initialized. Writing transmit data C Writing transmit data B Writing transmit data A C B A7 A6 A A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0 Start shift operation Start shift operation Start shift operation Clearing SIOS Reading received data Reading received data F Reading received data E Reading received data D F E D Writing transmit data SIO1CR<SIOS> SIO1SR<SIOF> SIO1SR<SEF> SCK1 pin output SO1 pin SI1 pin INTSIO1 interrupt request SIO1SR<TXF> SIO1SR<RXF> SIO1RDB SIO1TDB |
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