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TMP86FS49AIUG 数据表(PDF) 222 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 222 Page - Toshiba Semiconductor |
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222 / 296 page ![]() Page 206 16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.6 Data Transfer of I2C Bus TMP86FS49AIUG 16.6.3.1 When the MST is “1” (Master mode) Check the TRX and determine whether the mode is a transmitter or receiver. (1) When the TRX is “1” (Transmitter mode) Test the LRB. When the LRB is “1”, a receiver does not request data. Implement the process to generate a stop condition (Described later) and terminate data transfer. When the LRB is “0”, the receiver requests next data. When the next transmitted data is other than 8 bits, set the BC, set the ACK to “1”, and write the transmitted data to the SBIDBR. After writing the data, the PIN becomes “1”, a serial clock pulse is generated for transferring a next 1 word of data from the SCL pin, and then the 1 word of data is transmitted. After the data is transmitted, and an INTSBI interrupt request occurs. The PIN become “0” and the SCL pin is set to low level. If the data to be transferred is more than one word in length, repeat the procedure from the LRB test above. Figure 16-10 Example of when BC = “000”, ACK = “1” (2) When the TRX is “0” (Receiver mode) When the next transmitted data is other than of 8 bits, set the BC again. Set the ACK to “1” and read the received data from the SBIDBR (Reading data is undefined immediately after a slave address is sent). After the data is read, the PIN becomes “1”. A serial bus interface circuit outputs a serial clock pulse to the SCL pin to transfer next 1-word of data and sets the SDA pin to “0” at the acknowledge signal timing. An INTSBI interrupt request occurs and the PIN becomes “0”. Then a serial bus interface circuit outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that received data is read from the SBIDBR. Figure 16-11 Example of when BC = “000”, ACK = “1” D7 D6 2 3 4 5 6 7 8 9 D5 D4 D3 D2 D1 D0 1 Acknowledge signal from a receiver SCL pin SDA pin PIN INTSBI interrupt request Write to SBIDBR D7 D6 2 3 4 5 6 7 8 9 D5 D4 D3 D2 D1 New D7 D0 1 Acknowledge signal to a transmitter SCL pin SDA pin PIN INTSBI interrupt request Read SBIDBR |
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