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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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TMP86FS49AIUG 数据表(PDF) 218 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 218 Page - Toshiba Semiconductor |
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218 / 296 page  Page 202 16. Serial Bus Interface(I2C Bus) Ver.-D (SBI) 16.5 I2C Bus Control TMP86FS49AIUG When a stop condition on the bus or an arbitration lost is detected, the TRX is cleared to “0” by the hardware. " Table 16-2 TRX changing conditions in each mode " shows TRX changing conditions in each mode and TRX value after changing When a serial bus interface circuit operates in the free data format, a slave address and a direction bit are not recognized. They are handled as data just after generating a start condition. The TRX is not changed by a hard- ware. 16.5.7 Start/stop condition generation When the BB (Bit5 in SBISRB) is “0”, a slave address and a direction bit which are set to the SBIDBR are output on a bus after generating a start condition by writing “1” to the MST, TRX, BB and PIN. It is necessary to set ACK to “1” beforehand. Figure 16-5 Start Condition Generation and Slave Address Generation When the BB is “1”, sequence of generating a stop condition is started by writing “1” to the MST, TRX and PIN, and “0” to the BB. Do not modify the contents of MST, TRX, BB and PIN until a stop condition is gener- ated on a bus. When a stop condition is generated and the SCL line on a bus is pulled-down to low level by another device, a stop condition is generated after releasing the SCL line. Figure 16-6 Stop Condition Generation The bus condition can be indicated by reading the contents of the BB (Bit5 in SBISRB). The BB is set to “1” when a start condition on a bus is detected (Bus Busy State) and is cleared to “0” when a stop condition is detected (Bus Free State). 16.5.8 Interrupt service request and cancel When a serial bus interface circuit is in the master mode and transferring a number of clocks set by the BC and the ACK is complete, a serial bus interface interrupt request (INTSBI) is generated. Table 16-2 TRX changing conditions in each mode Mode Direction Bit Conditions TRX after Changing Slave Mode "0" A received slave address is the same value set to I2CAR "0" "1" "1" Master Mode "0" ACK signal is returned "1" "1" "0" Slave address and the direction bit Start condition Acknowledge signal A6 A5 2 3 4 5 6 7 8 9 A4 A3 A2 A1 A0 R/W 1 SCL pin SDA pin Stop condition SCL pin SDA pin |
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