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TMP86FS49AIUG 数据表(PDF) 223 Page - Toshiba Semiconductor

部件名 TMP86FS49AIUG
功能描述  8 Bit Microcontroller
PDF  296 Pages
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制造商  TOSHIBA [Toshiba Semiconductor]
网页  http://www.semicon.toshiba.co.jp/eng
标志 TOSHIBA - Toshiba Semiconductor

TMP86FS49AIUG 数据表(HTML) 223 Page - Toshiba Semiconductor

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TMP86FS49AIUG
To make the transmitter terminate transmit, clear the ACK to “0” before reading data which is 1-
word before the last data to be received. A serial bus interface circuit does not generate a clock pulse
for the acknowledge signal by clearing ACK. In the interrupt routine of end of transmission, when
the BC is set to “001” and read the data, PIN is set to “1” and generates a clock pulse for a 1-bit data
transfer. In this case, since the master device is a receiver, the SDA line on a bus keeps the high-
level. The transmitter receives the high-level signal as an ACK signal. The receiver indicates to the
transmitter that data transfer is complete.
After 1-bit data is received and an interrupt request has occurred, generate the stop condition to ter-
minate data transfer.
Figure 16-12 Termination of Data Transfer in Master Receiver Mode
16.6.3.2 When the MST is “0” (Slave mode)
In the slave mode, a serial bus interface circuit operates either in normal slave mode or in slave mode
after losing arbitration.
In the slave mode, the conditions of generating INTSBI interrupt request are follows:
• At the end of acknowledge sugnal when the received slave address matches to the value set by the
I2CAR
• At the end of acknowledge sugnal when a “GENERAL CALL” is received
• At the end of transferring or receiving after matching of slave address or receiving of “GENERAL
CALL”
A serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode. And an
INTSBI interrupt request occurs when word data transfer terminates after losing arbitration. The behavior
of INTSBI interrupt request and PIN after losing arbitration are shown in Table 16-3.
When an INTSBI interrupt request occurs, the PIN (bit 4 in the SBICRB) is reset, and the SCL pin is set
to low level. Either reading or writing from or to the SBIDBR or setting the PIN to “1” releases the SCL
pin after taking tLOW.
Table 16-3 The Behavior of INTSBI interrupt request and PIN after Losing Arbitration
When the Arbitration Lost Occurs during Trans-
mission of Slave Address as a Master
When the Arbitration Lost Occurs during Trans-
mission of Data as a Master Transmit Mode
INTSBI
interrupt
request
INTSBI interrupt request is generated at the termination of word data.
PIN
When the slave address matches the value set
by I2CAR, the PIN is cleared to "0" by generating
of INTSBI interrupt request. When the slave
address doesn't match the value set by I2CAR,
the PIN keeps "1".
PIN keeps "1" (PIN is not cleared to "0").
D7
D6
2
3
4
5
6
7
8
1
D5
D4
D2
D3
D1
D0
1
Acknowledge signal
sent to a transmitter
SCL pin
SDA pin
PIN
INTSBI
interrupt request
Clear ACK to "0"
before reading SBIDBR
Set BC to "001"
before reading SBIDBR



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