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ADE5166 数据表(PDF) 39 Page - Analog Devices |
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ADE5166 数据表(HTML) 39 Page - Analog Devices |
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39 / 148 page  Preliminary Technical Data ADE5166/ADE5169/ADE5566/ADE5569 Rev. PrB | Page 39 of 148 Bit Mnemonic Default Description 3 to 2 VARNOLOAD[1:0]1 00 Reactive Power No Load Threshold. VARNOLOAD[1:0] Result 00 No load detection disabled 01 No load detection enabled with threshold = 0.015% of full scale 10 No load detection enabled with threshold = 0.0075% of full scale 11 No load detection enabled with threshold = 0.0037% of full scale 1 to 0 APNOLOAD[1:0] 00 Active Power No Load Threshold. APNOLOAD[1:0] Result 00 No load detection disabled 01 No load detection enabled with threshold = 0.015% of full scale 10 No load detection enabled with threshold = 0.0075% of full scale 11 No load detection enabled with threshold = 0.0037% of full scale 1 This function is not available in the ADE5566 and ADE5166. Table 36. Accumulation Mode Register (ACCMODE, 0x0F) Bit Mnemonic Default Description 7 ICHANNEL1 0 This bit indicates the current channel used to measure energy in antitampering mode. 0 = Channel A 1 = Channel B 6 FAULTSIGN1 0 Configuration bit to select the event that triggers a fault interrupt. 0 = FAULTSIGN interrupt occurs when the part enters fault mode 1 = FAULTSIGN interrupt occurs when the part enters normal mode 5 VARSIGN2 0 Configuration bit to select the event that triggers a reactive power sign interrupt. If set to 0, VARSIGN interrupt occurs when reactive power changes from positive to negative. If set to 1, VARSIGN interrupt occurs when reactive power changes from negative to positive. 4 APSIGN 0 Configuration bit to select event that triggers an active power sign interrupt. If set to 0, APSIGN interrupt occurs when active power changes from positive to negative. If set to 1, APSIGN interrupt occurs when active power changes from negative to positive. 3 ABSVARM2 0 Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output. 2 SAVARM2 0 Logic 1 enables reactive power accumulation depending on the sign of the active power. If active power is positive, VAR is accumulated as it is. If active power is negative, the sign of the VAR is reversed for the accumulation. This accumulation mode affects both the VAR registers (VARHR, RVARHR, LVARHR) and the pulse output when connected to VAR.2 1 POAM 0 Logic 1 enables positive-only accumulation of active power in energy register and pulse output. 0 ABSAM 0 Logic 1 enables absolute value accumulation of active power in energy register and pulse output. 1 This function is not available in the ADE5566 and ADE5569. 2 This function is not available in the ADE5566 and ADE5166. Table 37. Gain Register (GAIN, 0x1B) Bit Mnemonic Default Description 7 to 5 PGA2[2:0] 000 These bits define the voltage channel input gain. PGA2[2:0] Result 000 Gain = 1 001 Gain = 2 010 Gain = 4 011 Gain = 8 100 Gain = 16 4 Reserved 0 Reserved. 3 CFSIGN_OPT 0 This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented. CFSIGN_OPT Result 0 Filtered power signal 1 On a per CF pulse basis |
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