ADE5166 datasheet(95/148 Pages) AD

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Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 95 of 148

Table 89. LCD Pointer SFR (LCDPTR, 0xAC)

Bit

Mnemonic

Default

Description

R/W

Read or write LCD bit. If this bit is set (1), the data in LCDDAT is written to the address indicated

by the LCDPTR[3:0] bits.

Reserved

Reserved.

5 to 4

RAM2SCREEN

These bits select the screen recipient of the data memory action.

3 to 0

ADDRESS

LCD memory address (see Table 92).

Table 90. LCD Data SFR (LCDDAT, 0xAE)

Bit

Mnemonic

Default

Description

7 to 0

LCDDATA

Data to be written into or read out of the LCD memory SFRs.

Table 91. LCD Segment Enable 2 SFR (LCDSEGE2, 0xED)

Bit

Mnemonic

Default

Description

7 to 4

Reserved

Reserved.

FP19EN

FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP18EN

FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP17EN

FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function.

FP16EN

FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function.

LCD SETUP

The LCD configuration SFR (LCDCON, 0x95) configures the

LCD module to drive the type of LCD in the user end system.

The BIAS and LMUX[1:0] bits in this SFR should be set according

to the LCD specifications.

The COM2/FP28 and COM3/FP27 pins default to LCD segment

lines. Selecting the 3× multiplex level in the LCD configuration

SFR (LCDCON, 0x95) by setting LMUX[1:0] to 10 changes the

FP28 pin functionality to COM2. The 4× multiplex level selection,

LMUX[1:0] = 11, changes the FP28 pin functionality to COM2

and the FP27 pin functionality to COM3.

The LCD segments, FP0 to FP15 and FP26, are enabled by

default. Additional pins are selected for LCD functionality in

the LCD segment enable SFR (LCDSEGE, 0x97) and LCD

Segment Enable 2 SFR (LCDSEGE2, 0xED) where there are

individual enable bits for the FP16 to FP25 segment pins. The

LCD pins do not have to be enabled sequentially. For example,

if the alternate function of FP23, the Timer 2 input, is required,

any of the other shared pins, FP16 to FP25, can be enabled

instead.

The Display Element Control section contains details about

setting up the LCD data memory to turn individual LCD

segments on and off. Setting the LCDRST bit in the LCD

configuration SFR (LCDCON, 0x95) resets the LCD data

memory to its default (0). A power-on reset also clears the

LCD data memory.

LCD TIMING AND WAVEFORMS

An LCD segment acts like a capacitor that is charged and

discharged at a certain rate. This rate, the refresh rate, determines

the visual characteristics of the LCD. A slow refresh rate results

in the LCD blinking on and off between refreshes. A fast refresh

rate presents a screen that appears to be continuously lit. In

addition, a faster refresh rate consumes more power.

The frame rate, or refresh rate, for the LCD module is derived

from the LCD clock, fLCDCLK. The LCD clock is selected as 2048 Hz

or 128 Hz by the CLKSEL bit in the LCD configuration SFR

(LCDCON, 0x95). The minimum refresh rate needed for the

LCD to appear solid (without blinking) is independent of the

multiplex level.

The LCD waveform frequency, fLCD, is the frequency at which

the LCD switches the active common line. Thus, the LCD

waveform frequency depends heavily on the multiplex level.

The frame rate and LCD waveform frequency are set by fLCDCLK,

the multiplex level, and the FD[3:0] frame rate selection bits in

the LCD clock SFR (LCDCLK, 0x96).

The LCD module provides 16 different frame rates for fLCDCLK =

2048 Hz, ranging from 8 Hz to 128 Hz for an LCD with 4×

multiplexing. Fewer options are available with fLCDCLK = 128 Hz,

ranging from 8 Hz to 32 Hz for a 4× multiplexed LCD. The

128 Hz clock is beneficial for battery operation because it

consumes less power than the 2048 Hz clock. The frame rate is

set by the FD[3:0] bits in the LCD clock SFR (LCDCLK, 0x96);

see Table 86 and Table 87.

The LCD waveform is inverted at twice the LCD waveform

frequency, fLCD. This way, each frame has an average dc offset

of zero. ADC offset degrades the lifetime and performance of

the LCD.

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