ADE5166 datasheet(41/148 Pages) AD

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Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 41 of 148

Table 41. Interrupt Status 2 SFR (MIRQSTM, 0xDD)

Bit

Interrupt Flag

Description

CF2

Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse output is not

enabled by clearing Bit 2 of the MODE1 register.

CF1

Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse output is not

enabled by clearing Bit 1 of the MODE1 register.

VAEOF

Logic 1 indicates that the VAHR register has overflowed.

REOF1

Logic 1 indicates that the VARHR register has overflowed.

AEOF

Logic 1 indicates that the WATTHR register has overflowed.

VAEHF

Logic 1 indicates that the VAHR register is half full.

REHF1

Logic 1 indicates that the VARHR register is half full.

AEHF

Logic 1 indicates that the WATTHR register is half full.

1 This function is not available in the ADE5566 and ADE5166.

Table 42. Interrupt Status 3 SFR (MIRQSTH, 0xDE)

Bit

Interrupt Flag

Description

RESET

Indicates the end of a reset (for both software and hardware reset).

Reserved

Reserved.

WFSM

Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).

PKI

Logic 1 indicates that current channel has exceeded the IPKLVL value

PKV

Logic 1 indicates that voltage channel has exceeded the VPKLVL value.

CYCEND

Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.

ZXTO

Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles.

Logic 1 indicates detection of a zero crossing in the voltage channel.

Table 43. Interrupt Enable 1 SFR (MIRQENL, 0xD9)

Bit

Interrupt Enable Bit

Description

7 to 6

Reserved

Reserved.

FAULTSIGN1

When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core.

VARSIGN2

When this bit is set, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.

APSIGN

When this bit is set, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.

VANOLOAD

When this bit is set, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.

RNOLOAD2

When this bit is set, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.

APNOLOAD

When this bit is set, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.

1 This function is not available in the ADE5566 and ADE5569.

2 This function is not available in the ADE5566 and ADE5166.

Table 44. Interrupt Enable 2 SFR (MIRQENM, 0xDA)

Bit

Interrupt Enable Bit

Description

CF2

When this bit is set, a CF2 pulse creates a pending ADE interrupt to the 8052 core.

CF1

When this bit is set, a CF1 pulse creates a pending ADE interrupt to the 8052 core.

VAEOF

When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.

REOF1

When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core.

AEOF

When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core.

VAEHF

When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.

REHF1

When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core.

AEHF

When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.

1 This function is not available in the ADE5566 and ADE5166.

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