ADE5166 datasheet(73/148 Pages) AD

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Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 73 of 148

8052 MCU CORE ARCHITECTURE

The ADE5166/ADE5169/ADE5566/ADE5569 has an 8052 MCU

core and uses the 8051 instruction set. Some of the standard

8052 peripherals, such as the UART, have been enhanced. This

section describes the standard 8052 core and enhancements

that have been made to it in the ADE5166/ADE5169/ADE5566/

ADE5569.

The special function register (SFR) space is mapped into the

upper 128 bytes of internal data memory space and is accessed

by direct addressing only. It provides an interface between the

CPU and all on-chip peripherals. A block diagram showing the

programming model of the ADE5166/ADE5169/ADE5566/

ADE5569 via the SFR area is shown in Figure 59.

All registers except the program counter (PC), instruction

in the SFR area. The SFR registers include control, configura-

tion, and data registers that provide an interface between the

CPU and all on-chip peripherals.

ENERGY

MEASUREMENT

62kB ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE

PROGRAM/DATA

MEMORY

8051-COMPATIBLE

CORE

2kB XRAM

OTHER ON-CHIP

PERIPHERALS:

SERIAL I/O

WDT

TIMERS

BATTERY

ADC

LCD DRIVER

TEMPERATURE

ADC

RTC

POWER

MANAGEMENT

128-BYTE

SPECIAL

FUNCTION

AREA

256 BYTES

GENERAL-

PURPOSE

RAM

BANKS

Figure 59: ADE5166/ADE5169/ADE5566/ADE5569 Block Diagram

MCU REGISTERS

The registers used by the MCU are summarized hereafter.

Table 56. 8051 SFRs

Table 57. Program Status Word SFR (PSW, 0xD0)

Bit

Address

Mnemonic

Description

0xD7

Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.

0xD6

Auxiliary Carry Flag. Modified by ADD, and ADDC instructions.

0xD5

General-Purpose Flag Available to the User.

4, 3

0xD4,

0xD3

RS1, RS0

RS1

RS0

Selected Bank

0xD2

Overflow Flag. Modified by ADD, ADDC, SUBB, MUL and DIV instructions.

0xD1

General-Purpose Flag Available to the User.

0xD0

Parity Bit. The number of bits set in the accumulator added to the value of the parity bit is always an

even number.

SFR

Address

Bit Addressable

Description

0xE0

Yes

Accumulator

0xF0

Yes

Auxiliary Math

PSW

0xD0

Yes

Program Status Word (see Table 57)

PCON

0x87

Power Control (see Table 58)

DPL

0x82

Data Pointer Low (see Table 59)

DPH

0x83

Data Pointer High (see Table 60)

DPTR

0x82 and 0x83

Data Pointer (see Table 61)

0x81

Stack Pointer (see Table 62)

SPH

0xB7

Stack Pointer High (see Table 63)

STCON

0xBF

Stack Boundary (see Table 64)

CFG

0xAF

Configuration (see Table 65)

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