ADE5166 datasheet(65/148 Pages) AD

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Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 65 of 148

The discrete time sample period (T) for the accumulation regis-

ter in the ADE5166/ADE5169/ADE5566/ADE5569 is 1.22 μs

(5/MCLK).

Figure 55 shows this discrete time integration or accumulation.

The apparent power signal is continuously added to the internal

energy theoretically remains positive.

The 49 bits of the internal register are divided by VADIV. If the

value in the VADIV register is 0, the internal apparent energy

The upper 24 bits are then written in the 24-bit apparent energy

provided to read the apparent energy. This register is reset to 0

after a read operation

Note that the apparent energy register is unsigned. By setting

the VAEHF and VAEOF bits in the Interrupt Enable 2 SFR

(MIRQENM, 0xDA), the ADE5166/ADE5169/ADE5566/

ADE5569 can be configured to issue an ADE interrupt to the

8052 core when the apparent energy register is half-full or when

an overflow occurs. The half-full interrupt for the unsigned

apparent energy register is based on 24 bits as opposed to 23 bits

for the signed active energy register.

Integration Times Under Steady Load: Apparent Energy

As mentioned in the Apparent Energy Calculation section, the

discrete time sample period (T) for the accumulation register is

1.22 μs (5/MCLK). With full-scale sinusoidal signals on the

analog inputs and the VAGAIN register set to 0x000, the

average word value from the apparent power stage is 0x1A36E2

(see the Apparent Power Calculation section). The maximum

value that can be stored in the apparent energy register before it

overflows is 224 or 0xFF,FFFF. The average word value is added

to the internal register, which can store 248 or 0xFFFF,FFFF,FFFF

before it overflows. Therefore, the integration time under these

conditions with VADIV = 0 is calculated as follows:

Time =

min

sec

199

0xD055

FFFF

FFFF,

0xFFFF,

(33)

When VADIV is set to a value different from 0, the integration

time varies, as shown in Equation 34.

Time = TimeWDIV = 0 × VADIV

(34)

Apparent Energy Pulse Output

All the ADE5166/ADE5169/ADE5566/ADE5569 circuitry has a

pulse output whose frequency is proportional to apparent power

(see the Energy-to-Frequency Conversion section). This pulse

frequency output uses the calibrated signal after VAGAIN. This

output can also be used to output a pulse whose frequency is

proportional to Irms.

The pulse output is active low and should preferably be connected

to an LED, as shown in Figure 58.

VADIV

APPARENT POWER

Irms

VAHR[23:0]

APPARENT POWER OR Irms IS

ACCUMULATED (INTEGRATED)

IN THE APPARENT ENERGY

TIME (nT)

APPARENT

POWER SIGNAL = P

Figure 55. Apparent Energy Calculation

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