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ADE5166 数据表(PDF) 97 Page - Analog Devices |
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ADE5166 数据表(HTML) 97 Page - Analog Devices |
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97 / 148 page ![]() Preliminary Technical Data ADE5166/ADE5169/ADE5566/ADE5569 Rev. PrB | Page 97 of 148 Table 92. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, 0xAC) and LCD Data SFR (LCDDAT, 0xAE)1,2 LCD Pointer SFR (LCDPTR, 0xAC) LCD Pointer SFR (LCDDAT, 0xAE) LCD Memory Address COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 0x0E FP28 FP28 FP28 FP28 0x0D FP27 FP27 FP27 FP27 FP26 FP26 FP26 FP26 0x0C FP25 FP25 FP25 FP25 FP24 FP24 FP24 FP24 0x0B FP23 FP23 FP23 FP23 FP22 FP22 FP22 FP22 0x0A FP21 FP21 FP21 FP21 FP20 FP20 FP20 FP20 0x09 FP19 FP19 FP19 FP19 FP18 FP18 FP18 FP18 0x08 FP17 FP17 FP17 FP17 FP16 FP16 FP16 FP16 0x07 FP15 FP15 FP15 FP15 FP14 FP14 FP14 FP14 0x06 FP13 FP13 FP13 FP13 FP12 FP12 FP12 FP12 0x05 FP11 FP11 FP11 FP11 FP10 FP10 FP10 FP10 0x04 FP9 FP9 FP9 FP9 FP8 FP8 FP8 FP8 0x03 FP7 FP7 FP7 FP7 FP6 FP6 FP6 FP6 0x02 FP5 FP5 FP5 FP5 FP4 FP4 FP4 FP4 0x01 FP3 FP3 FP3 FP3 FP2 FP2 FP2 FP2 0x00 FP1 FP1 FP1 FP1 FP0 FP0 FP0 FP0 1 COMx designates the common lines. 2 FPx designates the segment lines. VOLTAGE GENERATION The ADE5166/ADE5169/ADE5566/ADE5569 provide two ways to generate the LCD waveform voltage levels. The on-chip charge pump option can generate 5 V. This makes it possible to use 5 V LCDs with the 3.3 V ADE5166/ADE5169/ADE5566/ ADE5569. There is also an option to use an external resistor ladder with a 3.3 V LCD. The EXTRES bit in the LCD Configuration X SFR (LCDCONX, 0x9C) selects the resistor ladder or charge pump option. When selecting how to generate the LCD waveform voltages, the following should be considered: • Lifetime performance power consumption • Contrast control Lifetime Performance Power Consumption In most LCDs, a high amount of current is required when the LCD waveforms change state. The external resistor ladder option draws a constant amount of current, whereas the charge pump circuitry allows dynamic current consumption. If the LCD module is used with the internal charge pump option when the display is disabled, the voltage generation is disabled, so that no power is consumed by the LCD function. This feature results in significant power savings if the display is turned off during battery operation. Contrast Control The electrical characteristics of the liquid in the LCD change over temperature. This requires adjustments in the LCD waveform voltages to ensure a readable display. An added benefit of the internal charge pump voltage generation is a configurable bias voltage that can be compensated over temperature and supply to maintain contrast on the LCD. These compensations can be performed based on the ADE5166/ADE5169/ADE5566/ ADE5569 temperature and supply voltage measurements (see the Temperature, Battery, and Supply Voltage Measurements section). This dynamic contrast control is not easily imple- mented with external resistor ladder voltage generation. The LCD bias voltage sets the contrast of the display when the charge pump provides the LCD waveform voltages. The ADE5166/ ADE5169/ADE5566/ADE5569 provide 64 bias levels selected by the BIASLVL bits in the LCD Configuration X SFR (LCDCONX, 0x9C). The voltage level on LCDVA, LCDVB and LCDVC depend on the internal voltage reference value (VREF), BIASLVL[5:0] selection, and the biasing selected as described in Table 83. Lifetime Performance DC offset on a segment degrades its performance over time. The voltages generated through the internal charge pump switch faster than those generated by the external resistor ladder, reducing the likelihood of a dc voltage being applied to a segment and increasing the lifetime of the LCD. LCD EXTERNAL CIRCUITRY The voltage generation selection is made by Bit EXTRES in the LCD Configuration X SFR (LCDCONX, 0x9C). This bit is cleared by default for charge pump voltage generation, but can be set to enable an external resistor ladder. Charge Pump Voltage generation through the charge pump requires external capacitors to store charge. The external connections to LCDVA, LCDVB, and LCDVC, as well as LCDVP1 and LCDVP2, are shown in Figure 68. |
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