ADE5166 datasheet(92/148 Pages) AD

92 / 148 page

ADE5166/ADE5169/ADE5566/ADE5569

Preliminary Technical Data

Rev. PrB | Page 92 of 148

LCD DRIVER

Using shared pins, the LCD module is capable of directly driving

an LCD panel of 17 × 4 segments without compromising any

ADE5166/ADE5169/ADE5566/ADE5569 functions. It is capable

of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD

waveform voltages generated through internal charge pump

circuitry support up to 5 V LCDs. An external resistor ladder

for LCD waveform voltage generation is also supported.

Each ADE5166/ADE5169/ADE5566/ADE5569 has an embedded

LCD control circuit, driver, and power supply circuit. The LCD

module is functional in all operating modes (see the Operating

Modes section) and can store up to four different screens in

memory for scrolling purposes.

LCD REGISTERS

There are six LCD control registers that configure the driver for

the specific type of LCD in the end system and set up the user

display preferences. The LCD configuration SFR (LCDCON,

0x95), LCD Configuration X SFR (LCDCONX, 0x9C), and

LCD Configuration Y SFR (LCDCONY, 0xB1) contain general

LCD driver configuration information including the LCD enable

and reset, as well as the method of LCD voltage generation and

multiplex level. The LCD clock SFR (LCDCLK, 0x96) configures

timing settings for LCD frame rate and blink rate. LCD pins are

configured for LCD functionality in the LCD segment enable

SFR (LCDSEGE, 0x97) and the LCD Segment Enable 2 SFR

(LCDSEGE2, 0xED).

Table 80. LCD Driver SFRs

SFR Address

R/W

Mnemonic

Description

0x95

R/W

LCDCON

LCD configuration (see Table 81).

0x96

R/W

LCDCLK

LCD clock (see Table 85).

0x97

R/W

LCDSEGE

LCD segment enable (see Table 88).

0x9C

R/W

LCDCONX

LCD Configuration X (see Table 82).

0xAC

R/W

LCDPTR

LCD pointer (see Table 89).

0xAE

R/W

LCDDAT

LCD data (see Table 90).

0xB1

R/W

LCDCONY

LCD Configuration Y (see Table 84).

0xED

R/W

LCDSEGE2

LCD Segment Enable 2 (see Table 91).

Table 81. LCD Configuration SFR (LCDCON, 0x95)

Bit

Mnemonic

Value

Description

LCDEN

LCD enable. If this bit is set, the LCD driver is enabled.

LCDRST

LCD data registers reset. If this bit is set, the LCD data registers are reset to zero.

BLINKEN

Blink mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by the

BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD clock SFR (LCDCLK, 0x96).

LCDPSM2

Forces LCD off when in PSM2 (sleep mode). Note that the internal voltage reference must be enabled by

setting the REF_BAT_EN bit in the peripheral configuration SFR (PERIPH, 0xF4) to allow LCD operation

in PSM2.

LCDPSM2

Result

The LCD is disabled or enabled in PSM2 by the LCDEN bit.

The LCD is disabled in PSM2 regardless of LCDEN setting.

CLKSEL

LCD clock selection.

CLKSEL

Result

fLCDCLK = 2048 Hz

fLCDCLK = 128 Hz

BIAS

Bias mode.

BIAS

Result

1/2

1/3

1 to 0

LMUX[1:0]

LCD multiplex level.

LMUX[1:0]

Result

Reserved.

2× Multiplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as FP28.

3× Multiplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as COM2.

4× Multiplexing. FP27/COM3 is used as COM3. FP28/COM2 is used as COM2.

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