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ADE5166/ADE5169/ADE5566/ADE5569

Preliminary Technical Data

Rev. PrB | Page 30 of 148

3.3 V PERIPHERALS AND WAKE-UP EVENTS

Some of the 3.3 V peripherals are capable of waking the

ADE5166/ADE5169/ADE5566/ADE5569 from PSM2. The

events that can cause the ADE5166/ADE5169/ADE5566/

ADE5569 to wake up from PSM2 are listed in the Wake-Up

Event column in Table 28. The interrupt flag associated with

these events must be cleared prior to executing instructions that

put the ADE5166/ADE5169/ADE5566/ADE5569 in PSM2 mode

after wake-up.

Table 28. 3.3 V Peripherals and Wake-Up Events

3.3 V

Peripheral

Wake-

Event

Wake-Up

Enable Bits

Flag

Interrupt

Vector

Comments

Temperature

ADC

∆T

Maskable

ITADC

The temperature ADC can wake up the ADE5166/ADE5169/

ADE5566/ADE5569 if the ITADC flag is set. A pending interrupt is

generated according to the description in the Temperature

Measurement section. This wake-up event can be disabled by

disabling temperature measurements in the temperature and

supply delta SFR (DIFFPROG, 0xF3) in PSM2. The temperature

interrupt needs to be serviced and acknowledged prior to entering

PSM2 mode.

VDCIN ADC

ΔV

Maskable

FVADC

IPSM

The VDCIN measurement can wake up the ADE5166/ADE5169/

ADE5566/ADE5569. FVADC is set according to the description in

the External Voltage Measurement section. This wake-up event can

be disabled by clearing EVADC in the power management

interrupt enable SFR (IPSME, 0xEC); see Table 20. The FVADC flag

needs to be cleared prior to entering PSM2 mode.

Power Supply

Management

PSR

Nonmaskable

PSR

IPSM

The ADE5166/ADE5169/ADE5566/ADE5569 wake up if the power

supply is restored (if VSWOUT switches to be connected to VDD). The

VSWSOURCE flag, Bit 6 of the peripheral configuration SFR (PERIPH,

0xF4), is set to indicate that VSWOUT is connected to VDD.

RTC

Interval

Maskable

ITFLAG

IRTC

The ADE5166/ADE5169/ADE5566/ADE5569 wake up after the

programmable time interval has elapsed. The RTC interrupt needs

to be serviced and acknowledged prior to entering PSM2 mode.

Alarm

Maskable

Alarm

IRTC

An alarm can be set to wake the ADE5166/ADE5169/ADE5566/

ADE5569 after the desired amount of time. The RTC alarm is

enabled by setting the corresponding ALxx_EN bits in the RTC

Configuration 2 SFR (TIMECON2, 0xA2). The RTC interrupt needs to

be serviced and acknowledged prior to entering PSM2 mode.

I/O Ports1

INT0

INT0PRG = 1

IE0

The edge of the interrupt is selected by Bit IT0 in the TCON register. The

IE0 flag bit in the TCON register is not affected. The Interrupt 0

interrupt needs to be serviced and acknowledged prior to entering

PSM2 mode.

INT1

INT1PRG[2:0]

= 11x

IE1

The edge of the interrupt is selected by Bit IT1 in the TCON register. The

IE1 flag bit in the TCON register is not affected. The Interrupt 1

interrupt needs to be serviced and acknowledged prior to entering

PSM2 mode.

Rx Edge

RXPROG[1:0]

= 11

PERIPH[7]

(RXFG)

An Rx edge event occurs if a rising or falling edge is detected on

the Rx line. The UART RxD flag needs to be cleared prior to entering

PSM2 mode.

External Reset

RESET

Nonmaskable

If the RESET pin is brought low while the ADE5166/ADE5169/

ADE5566/ADE5569 is in PSM2, it wakes up to PSM1.

LCD

The LCD can be enabled/disabled in PSM2. The LCD data memory

remains intact.

Scratch Pad

The four SCRATCHx registers remain intact in PSM2.

1 All I/O pins are treated as inputs. The weak pull-up on each I/O pin can be disabled individually in the Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2), Port 1 Weak

Pull-Up Enable SFR (PINMAP1, 0xB3), and Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4) to decrease current consumption. The interrupts can be enabled/disabled.

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