 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADE5166 数据表(PDF) 93 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADE5166 数据表(HTML) 93 Page - Analog Devices |
|
|
93 / 148 page  Preliminary Technical Data ADE5166/ADE5169/ADE5566/ADE5569 Rev. PrB | Page 93 of 148 Table 82. LCD Configuration X SFR (LCDCONX, 0x9C) Bit Mnemonic Default Description 7 Reserved 0 Reserved. 6 EXTRES 0 External resistor ladder selection bit. EXTRES Result 0 External resistor ladder is disabled. Charge pump is enabled. 1 External resistor ladder is enabled. Charge pump is disabled. 5 to 0 BIASLVL[5:0] 0 Bias level selection bits (see Table 83). Table 83. LCD Bias Voltage When Contrast Control Is Enabled BIASLVL[5] VA (V) 1/2 Bias 1/3 Bias VB VC VB VC 0 [] 31 4:0 BIASLVL V REF × VB = VA VC = 2 × VA VB = 2 × VA VC = 3 × VA 1 [] ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + × 31 1 4:0 BIASLVL V REF VB = VA VC = 2 × VA VB = 2 × VA VC = 3 × VA Table 84. LCD Configuration Y SFR (LCDCONY, 0xB1) Bit Mnemonic Default Description 7 AUTOSCREENSCROLL 0 When set, the four screens scroll automatically. The scrolling item is selected by the BLKFREQ bits in the LCD clock SFR (LCDCLK, 0x96). If both BLINKEN and this bit are set, this bit preempt the blinking mode. 6 INV_LVL 0 Frame inversion mode enable bit. If this bit is set, frames are inverted every other frame. If this bit is cleared, frames are not inverted. 5 to 4 Reserved 00 These bits should be kept cleared for proper operation. 3 to 2 SCREEN_SEL These bits select the screen that is being output on the LCD pins. Values of 0, 1, 2, and 3 select screen 0, 1, 2, and 3, respectively 1 UPDATEOVER 0 Update finished flag bit. This bit is updated by the LCD driver. When set, this bit indicates that the LCD memory has been updated and a new frame has begun. 0 REFRESH 0 Refresh LCD data memory bit. This bit should be set by the user. When set, the LCD driver does not use the data in the LCD data registers to update the display. The LCD data registers can be updated by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display at the next frame. Table 85. LCD Clock SFR (LCDCLK, 0x96) Bit Mnemonic Default Description 7 to 6 BLKMOD[1:0] 0 Blink mode clock source configuration bits. BLKMOD[1:0] Result 00 The blink rate is controlled by software. The display is off. 01 The blink rate is controlled by software. The display is on. 10 The blink rate is 2 Hz. 11 The blink rate is set by BLKFREQ[1:0]. 5 to 4 BLKFREQ[1:0] 0 Blink rate configuration bits. These bits control the LCD blink rate if BLKMOD[1:0] = 11. BLKFREQ[1:0] Result (Blink Rate) 00 1 Hz 01 1/2 Hz 10 1/3 Hz 11 1/4 Hz 3 to 0 FD[3:0] 0 LCD frame rate selection bits (see Table 86 and Table 87). |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
