ADE5166 datasheet(29/148 Pages) AD

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Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 29 of 148

OPERATING MODES

PSM0 (NORMAL MODE)

In PSM0, normal operating mode, VSWOUT is connected to VDD.

All of the analog circuitry and digital circuitry powered by

VINTD and VINTA are enabled by default. In normal mode, the

default clock frequency, fCORE, established during a power-on

reset or software reset, is 1.024 MHz.

PSM1 (BATTERY MODE)

In PSM1, battery mode, VSWOUT is connected to VBAT.

In this operating mode, the 8052 core and all of the digital

circuitry are enabled by default. The analog circuitry for the

ADE energy metering DSP powered by VINTA is disabled. This

analog circuitry automatically restarts, and the switch to the

VDD power supply occurs when the VDD supply is above 2.75 V

and when the PWRDN bit in the MODE1 register (0x0B) is

cleared (see Table 32). The default fCORE for PSM1, established

during a power-on reset or software reset, is 1.024 MHz.

PSM2 (SLEEP MODE)

PSM2 is a low power consumption sleep mode for use in battery

operation. In this mode, VSWOUT is connected to VBAT. All of the

2.5 V digital and analog circuitry powered through VINTA and VINTD

are disabled, including the MCU core, resulting in the following:

•

The RAM in the MCU is no longer valid.

•

The program counter for the 8052, also held in volatile

memory, becomes invalid when the 2.5 V supply is shut

down. Therefore, the program does not resume from

where it left off but always starts from the power-on reset

vector when the ADE5166/ADE5169/ADE5566/ADE5569

exit PSM2.

The 3.3 V peripherals (temperature ADC, VDCIN ADC, RTC,

and LCD) are active in PSM2. They can be enabled or disabled

to reduce power consumption and are configured for PSM2

operation when the MCU core is active (see Table 28 for more

information about the individual peripherals and their PSM2

configuration). The ADE5166/ADE5169/ADE5566/ADE5569

remain in PSM2 until an event occurs to wake them up.

In PSM2, the ADE5166/ADE5169/ADE5566/ADE5569 provide

four scratch pad RAM SFRs that are maintained during this

mode. These SFRs can be used to save data from PSM0 or

PSM1 when entering PSM2 (see Table 21 to Table 24).

In PSM2, the ADE5166/ADE5169/ADE5566/ADE5569 main-

tain some SFRs (see Table 27). The SFRs that are not listed in

this table should be restored when the part enters PSM0 or

PSM1 from PSM2.

Table 27. SFR Maintained in PSM2

I/O Configuration

Power Supply Management

RTC Peripherals

LCD Peripherals

Interrupt Pins Configuration SFR

(INTPR, 0xFF), see Table 16

Battery Detection Threshold SFR

(BATVTH, 0xFA), see Table 52

RTC Nominal Compensation SFR

(RTCCOMP, 0xF6), see Table 123

LCD Segment Enable 2 SFR

(LCDSEGE2, 0xED), see Table 91

Peripheral Configuration SFR (PERIPH,

0xF4), see Table 19

Battery Switchover Configuration

SFR (BATPR, 0xF5), see Table 18

RTC Temperature Compensation

SFR (TEMPCAL, 0xF7),

see Table 124

LCD Configuration Y SFR

(LCDCONY, 0xB1), see Table 84

Port 0 Weak Pull-Up Enable SFR

(PINMAP0, 0xB2), see Table 156

Battery ADC Value SFR

(BATADC, 0xDF), see Table 54

RTC Configuration SFR (TIMECON,

0xA1), see Table 119

LCD Configuration X SFR

(LCDCONX, 0x9C), see Table 82

Port 1 Weak Pull-Up Enable SFR

(PINMAP1, 0xB3), see Table 157

Peripheral ADC Strobe Period SFR

(STRBPER, 0xF9), see Table 49

RTC Configuration 2 SFR

(TIMECON2, 0xA2), see Table 120

LCD Configuration SFR

(LCDCON, 0x95), see Table 81

Port 2 Weak Pull-Up Enable SFR

(PINMAP2, 0xB4), see Table 158

Temperature and Supply Delta SFR

(DIFFPROG, 0xF3), see Table 50

All indirectly accessible register

defined in the RTC register list. See

Table 126

LCD Clock SFR (LCDCLK, 0x96),

see Table 85

Scratch Pad 1 SFR (SCRATCH1, 0xFB),

see Table 21

VDCIN ADC Value SFR

(VDCINADC, 0xEF), see Table 53

LCD Segment Enable SFR

(LCDSEGE, 0x97) see Table 88

Scratch Pad 2 SFR (SCRATCH2, 0xFC),

see Table 22

Temperature ADC Value SFR

(TEMPADC, 0xD7), see Table 55

LCD Pointer SFR (LCDPTR, 0xAC),

see Table 89

Scratch Pad 3 SFR (SCRATCH3, 0xFD),

see Table 23

LCD Data SFR (LCDDAT, 0xAE),

see Table 90

Scratch Pad 4 SFR (SCRATCH4, 0xFE),

see Table 24

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