ADE5166 datasheet(26/148 Pages) AD

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ADE5166/ADE5169/ADE5566/ADE5569

Preliminary Technical Data

Rev. PrB | Page 26 of 148

Battery Switchover and Power Supply Restored

PSM Interrupt

The ADE5166/ADE5169/ADE5566/ADE5569 can be configured

to generate a PSM interrupt when the source of VSWOUT changes

from VDD to VBAT, indicating battery switchover. Setting the

EBSO bit in the power management interrupt enable SFR

(IPSME, 0xEC) enables this event to generate a PSM interrupt

(see Table 20).

The ADE5166/ADE5169/ADE5566/ADE5569 can also be

configured to generate an interrupt when the source of VSWOUT

changes from VBAT to VDD, indicating that the VDD power supply

has been restored. Setting the EPSR bit in the power management

interrupt enable SFR (IPSME, 0xEC) enables this event to generate

a PSM interrupt.

The flags in the IPSMF SFR for these interrupts, FBSO and

FPSR, are set regardless of whether the respective enable bits

have been set. The battery switchover and power supply restore

event flags, FBSO and FPSR, are latched. These events must be

cleared by writing a 0 to these bits. Bit 6 in the peripheral

configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the

source of VSWOUT. The bit is set when VSWOUT is connected to VDD

and cleared when VSWOUT is connected to VBAT.

VDCIN ADC PSM Interrupt

The ADE5166/ADE5169/ADE5566/ADE5569 can be configured

to generate a PSM interrupt when VDCIN changes magnitude by

more than a configurable threshold. This threshold is set in the

temperature and supply delta SFR (DIFFPROG, 0xF3), which is

described in Table 50. See the External Voltage Measurement

section for more information. Setting the EVDCIN bit in the

power management interrupt enable SFR (IPSME, 0xEC)

enables this event to generate a PSM interrupt.

The VDCIN voltage is measured using a dedicated ADC. These

measurements take place in the background at intervals to check

the change in VDCIN. Conversions can also be initiated by writing to

the start ADC measurement SFR (ADCGO, 0xD8) described in

Table 51. The FVDCIN flag indicates when a VDCIN measurement

is ready. See the External Voltage Measurement section for

details on how VDCIN is measured.

VBAT Monitor PSM Interrupt

The VBAT voltage is measured using a dedicated ADC. These

measurements take place in the background at intervals to

check the change in VBAT. The FBAT bit is set when the battery

level is lower than the threshold set in the battery detection

threshold SFR (BATVTH, 0xFA), described in Table 52, or

when a new measurement is ready in the battery ADC value

SFR (BATADC, 0xDF), described in Table 54. See the Battery

Measurement section for more information. Setting the EBAT

bit in the power management interrupt enable SFR (IPSME,

0xEC) enables this event to generate a PSM interrupt.

VDCIN Monitor PSM Interrupt

The VDCIN voltage is monitored by a comparator. The FVDCIN

bit in the power management interrupt flag SFR (IPSMF, 0xF8)

is set when the VDCIN input level is lower than 1.2 V. Setting the

EVDCIN bit in the IPSME SFR enables this event to generate a

PSM interrupt. This event, which is associated with the SAG

monitoring, can be used to detect a power supply (VDD) being

compromised and to trigger further actions prior to deciding a

switch of VDD to VBAT.

SAG Monitor PSM Interrupt

The ADE5166/ADE5169/ADE5566/ADE5569 energy measure-

ment DSP monitors the ac voltage input at the VP and VN input

pins. The SAGLVL register is used to set the threshold for a line

voltage SAG event. The FSAG bit in the power management

interrupt flag SFR (IPSMF, 0xF8) is set if the line voltage stays

below the level set in the SAGLVL register for the number of

line cycles set in the SAGCYC register. See the Line Voltage

SAG Detection section for more information. Setting the ESAG

bit in the power management interrupt enable SFR (IPSME,

0xEC) enables this event to generate a PSM interrupt.

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