ADE5166 datasheet(50/148 Pages) AD

50 / 148 page

ADE5166/ADE5169/ADE5566/ADE5569

Preliminary Technical Data

Rev. PrB | Page 50 of 148

can also be programmed to detect when the absolute value of

the line voltage drops below a certain peak value for a number

of line cycles. This condition is illustrated in Figure 35.

SAG RESET LOW

WHEN VOLTAGE

CHANNEL EXCEEDS

SAGLVL[15:0] AND

SAG FLAG RESET

FULL SCALE

SAGLVL[15:0]

SAG FLAG

SAGCYC[7:0] = 0x04

3 LINE CYCLES

VOLTAGE CHANNEL

Figure 35. SAG Detection

Figure 35 shows the line voltage falling below a threshold that

is set in the SAG level register (SAGLVL[15:0]) for three line

cycles. The quantities 0 and 1 are not valid for the SAGCYC

number of full line cycles. For example, when the SAG cycle

(SAGCYC[7:0]) contains 0x04, FSAG in the power management

interrupt flag SFR (IPSMF, 0xF8) is set at the end of the third

line cycle after the line voltage falls below the threshold. If the SAG

enable bit (ESAG) in the power management interrupt enable SFR

(IPSME, 0xEC) is set, the 8052 core has a pending power supply

management interrupt. The PSM interrupt stays active until the

ESAG bit is cleared (see the Power Supply Management Interrupt

(PSM) section).

In Figure 35, the SAG flag (FSAG) is set on the fifth line cycle

after the signal on the voltage channel first dropped below the

threshold level.

SAG Level Set

The 2-byte contents of the SAG level register (SAGLVL, 0x14)

are compared to the absolute value of the output from LPF1.

Therefore, when LPF1 is enabled, writing 0x2038 to the SAG

level register puts the SAG detection level at full scale (see

Figure 35). Writing 0x00 or 0x01 puts the SAG detection level

at 0. The SAG level register is compared to the input of the ZX

detection, and detection is made when the contents of the SAG

level register are greater.

Peak Detection

The ADE5166/ADE5169/ADE5566/ADE5569 can also be

programmed to detect when the absolute value of the voltage

or current channel exceeds a specified peak value. Figure 36

illustrates the behavior of the peak detection for the voltage

channel. Both voltage and current channels are monitored at

the same time.

PKV RESET

LOW WHEN

MIRQSTH SFR

IS READ

VPKLVL[15:0]

RESET BIT PKV

IN MIRQSTH SFR

PKV INTERRUPT

FLAG

Figure 36. Peak Level Detection

Figure 36 shows a line voltage exceeding a threshold that is set

in the voltage peak register (VPKLVL[15:0]). The voltage peak

event is recorded by setting the PKV flag in the Interrupt Status

3 SFR (MIRQSTH, 0xDE). If the PKV enable bit is set in the

Interrupt Enable 3 SFR (MIRQENH, 0xDB), the 8052 core has

a pending ADE interrupt. Similarly, the current peak event is

recorded by setting the PKI flag in Interrupt Status 3 SFR

(MIRQSTH, 0xDE). The ADE interrupt stays active until the

PKV or PKI status bit is cleared (see the Energy Measurement

Interrupts section).

Peak Level Set

The contents of the VPKLVL and IPKLVL registers are compared

to the absolute value of the voltage and 2 MSBs of the current

channel, respectively. Thus, for example, the nominal maximum

code from the current channel ADC with a full-scale signal is

0x28F5C2 (see the Current Channel ADC section). Therefore,

writing 0x28F5 to the IPKLVL register puts the current channel,

peak detection level at full scale and sets the current peak detec-

tion to its least sensitive value. Writing 0x00 puts the current

channel detection level at 0. The detection is done by comparing

the contents of the IPKLVL register to the incoming current

channel sample. The PKI flag indicates that the peak level is

exceeded. If the PKI or PKV bit is set in the Interrupt Enable 3

SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE

interrupt.

Peak Level Record

Each ADE5166/ADE5169/ADE5566/ADE5569 records the

maximum absolute value reached by the voltage and current

channels in two different registers, IPEAK and VPEAK,

respectively. Each register is a 24-bit unsigned register that is

updated each time the absolute value of the waveform sample

from the corresponding channel is above the value stored in the

VPEAK or IPEAK register. The contents of the VPEAK register

correspond to the maximum absolute value observed on the

voltage channel input. The contents of IPEAK and VPEAK

represent the maximum absolute value observed on the current

and voltage input, respectively. Reading the RSTVPEAK and

RSTIPEAK registers clears their respective contents after the read

operation.

ADE5166 数据表(PDF) 50 Page - Analog Devices

ADE5166 数据表(HTML) 50 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载