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ADE5166 数据表(PDF) 74 Page - Analog Devices |
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ADE5166 数据表(HTML) 74 Page - Analog Devices |
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74 / 148 page  ADE5166/ADE5169/ADE5566/ADE5569 Preliminary Technical Data Rev. PrB | Page 74 of 148 Table 58. Program Control SFR (PCON, 0x87) Bit Mnemonic Default Description 7 SMOD 0 Double baud rate control. 6 to 0 Reserved 0 Reserved, should be left cleared. Table 59. Data Pointer Low SFR (DPL, 0x82) Bit Mnemonic Default Description 7 to 0 DPH[7:0] 0 Contain the low byte of the data pointer. Table 60. Data Pointer High SFR (DPH, 0x83) Bit Mnemonic Default Description 7 to 0 DPH[7:0] 0 Contain the high byte of the data pointer. Table 61. Data Pointer SFR (DPTR, 0x82 and 0x83) Bit Mnemonic Default Description 15 to 0 DP[15:0] 0 Contain the 2-byte address of the data pointer. DPTR is a combination of DPH and DPL SFRs. Table 62. Stack Pointer SFR (SP, 0x81) Bit Mnemonic Default Description 7 to 0 SP[7:0] 0 Contain the eight LSBs of the pointer for the stack. Table 63. Stack Pointer High SFR (SPH, 0xB7) Bits Mnemonic Default Description 7 Reserved 1 Reserved. 6 SBFLG 0 Stack bottom flag. 5 SSA[10] 0 Stack Starting Address Bit 10. 4 SSA[9] 0 Stack Starting Address Bit 9. 3 SSA[8] 1 Stack Starting Address Bit 8. 2 SP[10] 0 Stack Address Bit 10. 1 SP[9] 0 Stack Address Bit 9. 0 SP[8] 1 Stack Address Bit 8. Table 64. Stack Boundary SFR (STCON, 0xBF) Bits Mnemonic Default Description 7 to 3 WTRLINE 0 Contains the stack water line setting bits. 2 INT_RST 0 Interrupt/reset selection bit. 0 An interrupt is issued when a stack violation occurs. 1 A reset is issued when a stack violation occurs. 1 SBE 0 Stack boundary enable bit. 0 WTRLFG 0 Waterline flag. Table 65. Configuration SFR (CFG, 0xAF) Bit Mnemonic Default Description 7 Reserved 1 This bit should be left set for proper operation. 6 EXTEN 0 Enhanced UART enable bit. EXTEN Result 0 Standard 8052 UART without enhanced error checking features 1 Enhanced UART with enhanced error checking—see the UART Additional Features section. 5 SCPS 0 Synchronous communication selection bit. SCPS Result 0 I2C port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs. 1 SPI port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs |
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