ADE5166 datasheet(55/148 Pages) AD

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Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 55 of 148

Active Power Gain Calibration

Figure 44 shows the signal processing chain for the active power

calculation in the ADE5166/ADE5169/ADE5566/ADE5569. As

explained previously, the active power is calculated by filtering

the output of the multiplier with a low-pass filter. Note that

when reading the waveform samples from the output of LPF2,

the gain of the active energy can be adjusted by using the

multiplier and watt gain register (WGAIN[11:0]). The gain is

adjusted by writing a twos complement 12-bit word to the watt

gain register. Equation 10 shows how the gain adjustment is

related to the contents of the watt gain register.

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

⎭

⎬

⎫

⎩

⎨

⎧ +

WGAIN

Power

Active

WGAIN

Output

(10)

For example, when 0x7FF is written to the watt gain register, the

power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5).

Similarly, 0x800 = −2048d (signed, twos complement) and power

output is scaled by –50%. Each LSB scales the power output by

0.0244%. The minimum output range is given when the watt

gain register contents are equal to 0x800 and the maximum

range is given by writing 0x7FF to the watt gain register. This

can be used to calibrate the active power (or energy) calculation

in the ADE5166/ADE5169/ADE5566/ADE5569.

Active Power Offset Calibration

The ADE5166/ADE5169/ADE5566/ADE5569 also incorporate

an active power offset register (WATTOS[15:0]). It is a signed,

twos complement, 16-bit register that can be used to remove

offsets in the active power calculation (see Figure 42). An offset

can exist in the power calculation due to crosstalk between

channels on the PCB or in the IC itself. The offset calibration

allows the contents of the active power register to be maintained

at 0 when no power is being consumed.

The 256 LSBs (WATTOS = 0x0100) written to the active power

offset register are equivalent to 1 LSB in the waveform sample

0xCCCCD (838,861d) when inputs on the voltage and current

channels are both at full scale. At −60 dB down on the current

channel (1/1000 of the current channel full-scale input), the

average word value output from LPF2 is 838.861 (838,861/1,000).

One LSB in the LPF2 output has a measurement error of

1/838.861 × 100% = 0.119% of the average value. The active

power offset register has a resolution equal to 1/256 LSB of

the waveform register. Therefore, the power offset correction

resolution is 0.000464%/LSB (0.119%/256) at −60 dB.

Active Power Sign Detection

The ADE5166/ADE5169/ADE5566/ADE5569 detect a change

of sign in the active power. The APSIGN flag in the Interrupt

Status 1 SFR (MIRQSTL, 0xDC) records when a change of sign

has occurred according to Bit APSIGN in the ACCMODE register

(0x0F). If the APSIGN flag is set in the Interrupt Enable 1 SFR

(MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt.

The ADE interrupt stays active until the APSIGN status bit is

cleared (see the Energy Measurement Interrupts section).

When APSIGN in the ACCMODE register (0x0F) is cleared

(default), the APSIGN flag in the Interrupt Status 1 SFR

(MIRQSTL, 0xDC) is set when a transition from positive–to-

negative active power has occurred.

When APSIGN in the ACCMODE register (0x0F) is set, the

APSIGN flag in the MIRQSTL SFR is set when a transition

from negative to positive active power occurs.

Active Power No Load Detection

The ADE5166/ADE5169/ADE5566/ADE5569 include a no load

threshold feature on the active energy that eliminates any creep

effects in the meter. The part accomplishes this by not accumulat-

ing energy if the multiplier output is below the no load threshold.

When the active power is below the no load threshold, the

APNOLOAD flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC)

is set. If the APNOLOAD bit is set in the Interrupt Enable 1 SFR

(MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt.

The ADE interrupt stays active until the APNOLOAD status bit is

cleared (see the Energy Measurement Interrupts section).

The no load threshold level is selectable by setting the

APNOLOAD bits in the NLMODE register (0x0E). Setting

these bits to 0b00 disables the no load detection, and setting

them to 0b01, 0b10, or 0b11 sets the no load detection threshold

to 0.015%, 0.0075%, or 0.0037% of the multiplier full-scale

output frequency, respectively. The IEC 62053-21 specification

states that the meter must start up with a load equal to or less

than 0.4% IPB, which translates to 0.0167% of the full-scale

output frequency of the multiplier.

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