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Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 85 of 148

INTERRUPT SYSTEM

The unique power management architecture of the ADE5166/

ADE5169/ADE5566/ADE5569 includes an operating mode

(PSM2) where the 8052 MCU core is shut down. Events can

be configured to wake the 8052 MCU core from the PSM2

operating mode. A distinction is drawn here between events

that can trigger the wake-up of the 8052 MCU core and events

that can trigger an interrupt when the MCU core is active.

Events that can wake the core are referred to as wake-up events,

whereas events that can interrupt the program flow when the

MCU is active are called interrupts. See the 3.3 V Peripherals

and Wake-Up Events section to learn more about events that

can wake the 8052 core from PSM2.

The ADE5166/ADE5169/ADE5566/ADE5569 provide 12 inter-

rupt sources with three priority levels. The power management

interrupt is at the highest priority level. The other two priority

levels are configurable through the interrupt priority SFR (IP,

0xB8) and interrupt enable and Priority 2 SFR (IEIP2, 0xA9).

STANDARD 8052 INTERRUPT ARCHITECTURE

The 8052 standard interrupt architecture includes two tiers of

interrupts, where some interrupts are assigned a high priority

and others are assigned a low priority.

PRIORITY 1

PRIORITY 0

HIGH

LOW

Figure 65. Standard 8052 Interrupt Priority Levels

A Priority 1 interrupt can interrupt the service routine of a

Priority 0 interrupt, and if two interrupts of different priorities

occur at the same time, the Priority 1 interrupt is serviced first.

An interrupt cannot be interrupted by another interrupt of the

same priority level. If two interrupts of the same priority level

occur simultaneously, a polling sequence is observed (see the

Interrupt Priority section).

INTERRUPT ARCHITECTURE

The ADE5166/ADE5169/ADE5566/ADE5569 possess advanced

power supply management features. To ensure a fast response to

time-critical power supply issues, such as a loss of line power,

the power supply management interrupt should be able to inter-

rupt any interrupt service routine. To enable the user to have

full use of the standard 8052 interrupt priority levels, an additional

priority level is added for the power supply management (PSM)

interrupt. The PSM interrupt is the only interrupt at this highest

interrupt priority level.

PRIORITY 1

PRIORITY 0

PSM

HIGH

LOW

Figure 66. Interrupt Architecture

See the Power Supply Management Interrupt (PSM) section for

more information on the PSM interrupt.

INTERRUPT REGISTERS

The control and configuration of the interrupt system is carried

out through four interrupt-related SFRs, discussed in this section.

Table 70. Interrupt SFRs

SFR

Address

Default

Bit Addressable

Description

0xA8

0x00

Yes

Interrupt enable (see Table 71).

0xB8

0x00

Yes

Interrupt priority (see Table 72).

IEIP2

0xA9

0xA0

Interrupt enable and Priority 2 (see Table 73).

WDCON

0xC0

0x10

Yes

Watchdog timer (see Table 78 and the Writing to the Watchdog Timer SFR

(WDCON, 0xC0) section).

Table 71. Interrupt Enable SFR (IE, 0xA8)

Bit

Address

Mnemonic

Description

0xAF

Enables all interrupt sources. Set by the user. Cleared by the user to disable all interrupt sources.

0xAE

ETEMP

Enables the temperature ADC interrupt. Set by the user.

0xAD

ET2

Enables the Timer 2 interrupt. Set by the user.

0xAC

Enables the UART serial port interrupt. Set by the user.

0xAB

ET1

Enables the Timer 1 interrupt. Set by the user.

0xAA

EX1

Enables the External Interrupt 1 (INT1). Set by the user.

0xA9

ET0

Enables the Timer 0 interrupt. Set by the user.

0xA8

EX0

Enables External Interrupt 0 (INT0). Set by the user.

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