ADE5166 datasheet(77/148 Pages) AD

77 / 148 page

Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 77 of 148

the stack boundary protection is enabled and fixed to issue an

interrupt should an event occur. STCON[1] and STCON[2] can

therefore not be altered when the protection bit is set. Once the

protection bit is set, the default stack starting address, SPH[5:3],

can only be written once before becoming fixed. It is therefore

recommended that this feature be configured for the application

before the stack boundary protection bit is written in the flash.

0xFF

0x7FF

256 BYTES

OF RAM

(DATA)

0x00

{SPH[5:3], 0x00}

0x7FF-STCON[7:3]

2kB OF

ON-CHIP x-RAM

STACK STARTING

ADDRESS

WATERLINE

0x00

Figure 60. Extended Stack Pointer Operation

STANDARD 8052 SFRS

The standard 8052 special function registers include the accumula-

tor, B, PSW, DPTR, and SP SFRs described in the Basic 8052

Registers section. The 8052 also defines standard timers, serial

port interfaces, interrupts, I/O ports and power down modes.

Timer SFRs

The 8052 contains three 16-bit timers, the identical Timer0 and

Timer1, as well as a Timer2. These timers can also function as

event counters. Timer2 has a capture feature where the value

of the timer can be captured in two 8-bit registers upon the

assertion of an external input signal (see the Timers section).

Serial Port SFRs

The two full-duplex serial port peripherals each require two

registers, one for setting up the baud rate and other communica-

tion parameters, and another byte for the transmit/receive

buffer. TheADE5166/ADE5169/ADE5566/ADE5569 also

provide enhanced serial port functionality with a dedicated

timer for baud rate generation with a fractional divisor and

additional error detection. See the UART Serial Interface

section and the UART2 Serial Interface section for details.

Interrupt SFR

There is a two-tiered interrupt system standard in the 8052

core. The priority level for each interrupt source is individually

selectable as high or low. The TheADE5166/ADE5169/ADE5566/

ADE5569 enhance this interrupt system by creating in essence a

third interrupt tier for a highest priority power supply manage-

ment interrupt, PSM (see the Interrupt System section).

I/O Port SFRs

The 8052 core supports four I/O ports, P0 through P3, where

Port 0 and Port 2 are typically used for access to external code

and data spaces. The ADE5166/ADE5169/ADE5566/ADE5569,

unlike standard 8052 products, provide internal nonvolatile

Flash memory so that an external code space is unnecessary.

The on-chip LCD driver requires many pins, some of which are

dedicated for LCD functionality and others that can be configured

at LCD or general-purpose I/O. Due to the limited number of

I/O pins, the ADE5166/ADE5169/ADE5566/ADE5569 do not

allow access to external code and data spaces.

The ADE5166/ADE5169/ADE5566/ADE5569 provide 20 pins

that can be used for general purpose I/O. These pins are mapped

to Port 0, Port 1, and Port 2, and are accessed through three

bit-addressable 8052 SFRs: P0, P1, and P2. Another enhanced

feature of the ADE5166/ADE5169/ADE5566/ADE5569 is that

the weak pull-ups standard on 8052 Port 1, Port 2, and Port 3

can be disabled to make open-drain outputs, as is standard on

Port 0. The weak pull-ups can be enabled on a pin-by-pin basis

(see the I/O Ports section).

Power Control Register (PCON, 0x87)

The 8052 core defines two power-down modes; power-down

and idle. The ADE5166/ADE5169/ADE5566/ADE5569

enhance the power control capability of the traditional 8052

MCU with additional power management functions. The

POWCON register is used to define power control specific

functionality for the ADE5166/ADE5169/ADE5566/ADE5569.

The program control SFR (PCON, 0x87) is not bit addressable

(see Power Management section).

The ADE5166/ADE5169/ADE5566/ADE5569 provide many

other peripherals not standard to the 8052 core.

•

ADE energy measurement DSP

•

Full RTC

•

LCD driver

•

Battery switchover/power management

•

Temperature ADC

•

Battery ADC

•

SPI/I2C communication

•

Flash memory controller

•

Watchdog timer

•

Secondary UART port

MEMORY OVERVIEW

The ADE5166/ADE5169/ADE5566/ADE5569 contain three

memory blocks.

•

62 kB of on-chip Flash/EE program and data memory

•

256 bytes of general-purpose RAM

•

2 kB of internal extended RAM (XRAM)

The 256 bytes of general-purpose RAM shares the upper 128 bytes

of its address space with special function registers. All of the

memory spaces are shown in Figure 59. The addressing mode

specifies which memory space to access.

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