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HD64F2149YV 数据表(PDF) 367 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 367 Page - Renesas Technology Corp |
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367 / 1075 page ![]() Section 11 16-Bit Free-Running Timer Rev. 3.00 Jan 18, 2006 page 339 of 1044 REJ09B0280-0300 11.6 Usage Notes Application programmers should note that the following types of contention can occur in the free- running timer. Contention between FRC Write and Clear: If an internal counter clear signal is generated during the state after an FRC write cycle, the clear signal takes priority and the write is not performed. Figure 11.18 shows this type of contention. T1 T2 FRC write cycle Address FRC address Internal write signal φ Counter clear signal FRC N H'0000 Figure 11.18 FRC Write-Clear Contention |
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