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HD64F2149YV 数据表(PDF) 368 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 368 Page - Renesas Technology Corp |
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368 / 1075 page ![]() Section 11 16-Bit Free-Running Timer Rev. 3.00 Jan 18, 2006 page 340 of 1044 REJ09B0280-0300 Contention between FRC Write and Increment: If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 11.19 shows this type of contention. T1 T2 FRC write cycle Address Internal write signal φ FRC input clock FRC N M Write data FRC address Figure 11.19 FRC Write-Increment Contention |
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