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HD64F2149YV 数据表(PDF) 110 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 110 Page - Renesas Technology Corp |
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110 / 1075 page ![]() Section 3 MCU Operating Modes Rev. 3.00 Jan 18, 2006 page 82 of 1044 REJ09B0280-0300 Bit 6—IOS Enable (IOSE): Controls the function of the AS/IOS pin in expanded mode. Bit 6 IOSE Description 0 The AS/IOS pin functions as the address strobe pin (Low output when accessing an external area) (Initial value) 1 The AS/IOS pin functions as the I/O strobe pin (Low output when accessing a specified address from H'(FF)F000 to H'(FF)F7FF) Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow. Bit 3 XRST Description 0 A reset is generated by watchdog timer overflow 1 A reset is generated by an external reset (Initial value) Bit 1—Host Interface Enable (HIE): This bit controls CPU access to the host interface (HIF:XBS) data registers and control registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2), the keyboard controller and MOS input pull-up control registers (KMIMR, KMPCR, and KMIMRA), the 8-bit timer (channel X and Y) data registers and control registers (TCRX/TCRY, TCSRX/TCSRY, TICRR/TCORAY, TICRF/TCORBY, TCNTX/TCNTY, TCORC/TISR, TCORAX, and TCORBX), and the timer connection control registers (TCONRI, TCONRO, TCONRS, and SEDGR). Bit 1 HIE Description 0 In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to 8-bit timer (channel X and Y) data registers and control registers, and timer connection control registers, is permitted (Initial value) 1 In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to host interface data registers and control registers, and keyboard controller and MOS input pull-up control registers, is permitted |
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