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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HD64F2149YV 数据表(PDF) 113 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 113 Page - Renesas Technology Corp |
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113 / 1075 page  Section 3 MCU Operating Modes Rev. 3.00 Jan 18, 2006 page 85 of 1044 REJ09B0280-0300 Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), the power-down mode control registers (SBYCR, LPWRCR, MSTPCRH, and MSTPCRL), and the supporting module control register (PCSR and SYSCR2). Bit 3 FLSHE Description 0 Addresses H'(FF)FF80 to H'(FF)FF87 are used for power-down mode control register and supporting module control register access (Initial value) 1 Addresses H'(FF)FF80 to H'(FF)FF87 are used for flash memory control register access Bit 2—Reserved: Do not write 1 to this bit. Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12, 8-Bit Timers. |
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