HD64F2149YV datasheet(170/1075 Pages) RENESAS

170 / 1075 page

Section 6 Bus Controller

Rev. 3.00 Jan 18, 2006 page 142 of 1044

REJ09B0280-0300

6.2

6.2.1

Bus Control Register (BCR)

ICIS1

R/W

ICIS0

R/W

BRSTRM

R/W

BRSTS1

R/W

BRSTS0

R/W

IOS0

R/W

—

R/W

IOS1

R/W

Bit

Initial value

Read/Write

BCR is an 8-bit readable/writable register that specifies the external memory space access mode,

and the extent of the I/O area when the I/O strobe function has been selected for the

AS pin.

BCR is initialized to H'D7 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Idle Cycle Insert 1 (ICIS1): Reserved. Do not write 0 to this bit.

Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not a one-state idle cycle is to be inserted

between bus cycles when successive external read and external write cycles are performed.

Bit 6

ICIS0

Description

Idle cycle not inserted in case of successive external read and external write cycles

Idle cycle inserted in case of successive external read and external write cycles

(Initial value)

Bit 5—Burst ROM Enable (BRSTRM): Selects whether external space is designated as a burst

ROM interface space. The selection applies to the entire external space .

Bit 5

BRSTRM

Description

Basic bus interface

(Initial value)

Burst ROM interface

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