HD64F2149YV datasheet(171/1075 Pages) RENESAS

171 / 1075 page

Section 6 Bus Controller

Rev. 3.00 Jan 18, 2006 page 143 of 1044

REJ09B0280-0300

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM

interface.

Bit 4

BRSTS1

Description

Burst cycle comprises 1 state

Burst cycle comprises 2 states

(Initial value)

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a

burst ROM interface burst access.

Bit 3

BRSTS0

Description

Max. 4 words in burst access

(Initial value)

Max. 8 words in burst access

Bit 2—Reserved: Do not write 0 to this bit.

Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): See table 6.4.

6.2.2

Wait State Control Register (WSCR)

RAMS

R/W

RAM0

R/W

ABW

R/W

AST

R/W

WMS1

R/W

WC0

R/W

WMS0

R/W

WC1

R/W

Bit

Initial value

Read/Write

WSCR is an 8-bit readable/writable register that specifies the data bus width, number of access

states, wait mode, and number of wait states for external memory space. The on-chip memory and

internal I/O register bus width and number of access states are fixed, irrespective of the WSCR

settings.

WSCR is initialized to H'33 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—RAM Select (RAMS)/Bit 6—RAM Area Setting (RAM0): Reserved bits. Do not write

1 to these bits.

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