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HD64F2149YV 数据表(PDF) 229 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 229 Page - Renesas Technology Corp |
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229 / 1075 page ![]() Section 8 I/O Ports Rev. 3.00 Jan 18, 2006 page 201 of 1044 REJ09B0280-0300 Expanded Modes Single-Chip Mode Port Description Pins Mode 1 Mode 2, Mode 3 (EXPE = 1) Mode 2, Mode 3 (EXPE = 0) Port 8 • 7-bit I/O port P86/ IRQ5/SCK1/ SCL1 P85/ IRQ4/RxD1 P84/ IRQ3/TxD1 P83/ LPCPD P82/HIFSD/ CLKRUN P81/ CS2/GA20 P80/HA0/ PME I/O port also functioning as external interrupt input ( IRQ5, IRQ4, IRQ3), SCI1 input/ output (TxD1, RxD1, SCK1), and I 2C bus interface 1 input/output (SCL1) I/O port also functioning as external interrupt input ( IRQ5, IRQ4, IRQ3), SCI1 input/output (TxD1, RxD1, SCK1), host interface (XBS) control input/output ( CS2, GA20, HA0, HIFSD), host interface (LPC) control input/output ( LPCPD, CLKRUN, GA20, PME), and I2C bus interface 1 input/output (SCL1) Port 9 • 8-bit I/O port P97/ WAIT/SDA0 I/O port also functioning as expanded data bus control input ( WAIT) and I2C bus interface 0 input/output (SDA0) I/O port also functioning as I 2C bus interface 0 input/output (SDA0) P96/ φ/EXCL When DDR = 0: input port or EXCL input When DDR = 1 (after reset): φ output When DDR = 0 (after reset): input port or EXCL input When DDR = 1: φ output P95/ AS/IOS/CS1 P94/ HWR/IOW P93/ RD/IOR Expanded data bus control output ( AS/IOS, HWR, RD) I/O port also functioning as host interface (XBS) control input ( CS1, IOW, IOR) |
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