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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HD64F2149YV 数据表(PDF) 306 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 306 Page - Renesas Technology Corp |
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306 / 1075 page  Section 8 I/O Ports Rev. 3.00 Jan 18, 2006 page 278 of 1044 REJ09B0280-0300 Port G Data Direction Register (PGDDR) Bit 7 6543 210 PG7DDR PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Initial value 0 0000 000 Read/Write W WWWW WWW PGDDR is an 8-bit write-only register, the individual bits of which select input or output for the pins of port G. PGDDR is at the same address as PGPIN, and if read, will return the port G pin states. Setting a PGDDR bit to 1 makes the corresponding pins on port G an output pin, while clearing the bit to 0 makes the pin an input pin. PGDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port G Output Data Register (PGODR) Bit 7 6543 210 PG7ODR PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR Initial value 0 0000 000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PGODR is an 8-bit read/write register that stores output data for the pins on port G (PG7 to PG0). PGODR can always be read from or written to, regardless of the PGDDR settings. PGODR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port G Input Data Register (PGPIN) Bit 7 6543 210 PG7PIN PG6PIN PG5PIN PG4PIN PG3PIN PG2PIN PG1PIN PG0PIN Initial value —* —* —* —* —* —* —* —* Read/Write R RRRR RRR Note: * Determined by the state of pins PG7 to PG0. Reading PGPIN always returns the pin states. |
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