| 数据搜索系统,热门电子元器件搜索 |
|
HD64F2149YV 数据表(PDF) 307 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD64F2149YV 数据表(HTML) 307 Page - Renesas Technology Corp |
|
307 / 1075 page ![]() Section 8 I/O Ports Rev. 3.00 Jan 18, 2006 page 279 of 1044 REJ09B0280-0300 PGPIN is at the same address as PGDDR. Writing is to PGDDR and the port G settings will change unless the given byte represents the current settings. Port G Nch-OD Control Register (PGNOCR) Bit 7 6543 210 PG7NOC PG6NOC PG5NOC PG4NOC PG3NOC PG2NOC PG1NOC PG0NOC Initial value 0 0000 000 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PGNOCR is an 8-bit read/write register, the individual bits of which specify the output driver type for pins on port G which are configured as outputs. Setting a PENOCR or PFNOCR bit to 1 disables the P-channel driver for the corresponding pin on port G. Clearing the bit to 0 enables the P-channel driver for the pin. Although the P-channel drivers are always connected, the output driver type will look like CMOS when the bit is cleared to 0 and N-channel open-drain when it is set to 1. PGNOCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. DDR 0 1 NOCR — 01 ODR 0 1 010 1 N-ch. driver OFF ON OFF ON OFF P-ch. driver OFF OFF ON OFF MOS Input Pul-Up OFF ON OFF |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |