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Data Sheet

ADV7340/ADV7341

Rev. C | Page 31 of 108

A microprocessor can read from or write to all registers of the

ADV7340/ADV7341 via the MPU port, except for registers that

are specified as read-only or write-only registers.

The subaddress register determines which register the next

read or write operation accesses. All communication through

the MPU port starts with an access to the subaddress register.

A read/write operation is then performed from/to the target

address, which increments to the next address until the

transaction is complete.

Table 17 to Table 35 describe the functionality of each register.

All registers can be read from as well as written to, unless

otherwise stated.

SUBADDRESS REGISTER (SR7 TO SR0)

The subaddress register is an 8-bit write-only register. After the

MPU port is accessed and a read/write operation is selected, the

subaddress is set up. The subaddress register determines to or

from which register the operation takes place.

Table 17. Register 0x00

SR7 to

SR0

Bit Description

Bit Number

Setting

Reset

Value

0x00

Power

mode

Sleep mode. With this control enabled, the current

consumption is reduced to µA level. All DACs and the internal

PLL circuits are disabled. Registers can be read from and

written to in sleep mode.

Sleep

mode off

0x12

Sleep

mode on

PLL and oversampling control. This control allows the internal

PLL 1 circuit to be powered down and the oversampling to be

switched off.

PLL 1 on

PLL 1 off

DAC 3: power on/off.

DAC 3 off

DAC 3 on

DAC 2: power on/off.

DAC 2 off

DAC 2 on

DAC 1: power on/off.

DAC 1 off

DAC 1 on

DAC 6: power on/off.

DAC 6 off

DAC 6 on

DAC 5: power on/off.

DAC 5 off

DAC 5 on

DAC 4: power on/off.

DAC 4 off

DAC 4 on

Table 18. Register 0x01 to Register 0x09

SR7 to

Bit Number1

Reset

SR0

Bit Description

Value

0x01

Mode select

Reserved.

0x00

DDR clock edge alignment

(only used for ED2 and HD

DDR modes)

Chroma clocked in on rising clock edge;

luma clocked in on falling clock edge

Reserved

Luma clocked in on rising clock edge;

chroma clocked in on falling clock edge

Reserved.

Input mode (see Subaddress

0x30, Bits[7:3] for ED/HD

standard selection)

SD input only

ED/HD-SDR input only

ED/HD-DDR input only

SD and ED/HD-SDR

SD and ED/HD-DDR

Reserved

ED only (at 54 MHz)

Y/C/S bus swap

Allows data to be applied to data ports in

various configurations (SD feature only)

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