ADV7341_15 datasheet(56/108 Pages) AD

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ADV7340/ADV7341

Data Sheet

Rev. C | Page 56 of 108

SD SUBCARRIER FREQUENCY CONTROL

Subaddress 0x8C to Subaddress 0x8F

The ADV7340/ADV7341 is able to generate the color subcarrier

used in CVBS and S-Video (Y-C) outputs from the input pixel

clock. Four 8-bit registers are used to set up the subcarrier

frequency. The value of these registers is calculated using

MHz

line

video

one

cycles

clk

Number

line

video

one

periods

subcarrier

Number

Frequency

Subcarrier

where the sum is rounded to the nearest integer. For example, in

NTSC mode

569408543

1716

227













Value

Subcarrier

where:

Subcarrier Register Value = 569408543d = 0×21F07C1F

SD FSC Register 0: 0x1F

SD FSC Register 1: 0x7C

SD FSC Register 2: 0xF0

SD FSC Register 3: 0x21

Programming the FSC

The subcarrier frequency register value is divided into four FSC

registers, as shown in the previous example. The four subcarrier

frequency registers must be updated sequentially, starting with

Subcarrier Frequency Register 0 and ending with Subcarrier

Frequency Register 3. The subcarrier frequency updates only

after the last subcarrier frequency register byte is received by

the ADV7340/ADV7341. The SD input standard autodetection

feature must be disabled.

Typical FSC Values

Table 42 outlines the values that should be written to the

subcarrier frequency registers for NTSC and PAL B/D/G/H/I.

Table 42. Typical FSC Values

Subaddress

Description

NTSC

PAL B/D/G/H/I

0x8C

FSC0

0x1F

0xCB

0x8D

FSC1

0x7C

0x8A

0x8E

FSC2

0xF0

0x09

0x8F

FSC3

0x21

0x2A

SD NONINTERLACED MODE

Subaddress 0x88, Bit 1

The ADV7340/ADV7341 support an SD noninterlaced mode.

Using this mode, progressive inputs at twice the frame rate of

NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively)

can be input into the ADV7340/ADV7341. The SD noninter-

laced mode can be enabled using Subaddress 0x88, Bit 1.

A 27 MHz clock signal must be provided on the CLKIN_A pin.

Embedded EAV/SAV timing codes or external horizontal and

vertical synchronization signals provided on the S_HSYNC and

S_VSYNC pins can be used to synchronize the input pixel data.

All input configurations, output configurations, and features

available in NTSC and PAL modes are available in SD noninter-

laced mode. For 240p/59.94 Hz input, the ADV7340/ADV7341

should be configured for NTSC operation, and Subaddress

0x88, Bit 1 should be set to 1.

For 288p/50 Hz input, the ADV7340/ADV7341 should be con-

figured for PAL operation, and Subaddress 0x88, Bit 1 should be

set to 1.

SD SQUARE PIXEL MODE

Subaddress 0x82, Bit 4

The ADV7340/ADV7341 support an SD square pixel mode

(Subaddress 0x82, Bit 4). For NTSC operation, an input clock of

24.5454 MHz is required. The active resolution is 640 × 480. For

PAL operation, an input clock of 29.5 MHz is required. The

active resolution is 768 × 576.

For CVBS and S-Video (Y-C) outputs, the SD subcarrier

frequency registers must be updated to reflect the input clock

frequency used in SD square pixel mode. The SD input standard

autodetection feature must be disabled in SD square pixel

mode. In square pixel mode, the timing diagrams shown in

Figure 60 and Figure 61 apply.

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