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ADV7341 数据表(PDF) 16 Page - Analog Devices |
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ADV7341 数据表(HTML) 16 Page - Analog Devices |
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16 / 108 page  ADV7340/ADV7341 Data Sheet Rev. C | Page 16 of 108 Figure 10. SD, ED/HD-SDR Input Mode, 16-/20-Bit, 4:2:2 ED/HD and 8-/10-Bit, SD Pixel Input Mode (Input Mode 011) Figure 11. SD, ED/HD-DDR Input Mode, 8-/10-Bit, 4:2:2 ED/HD and 8-/10-Bit, SD Pixel Input Mode (Input Mode 100) Figure 12. ED Only (at 54 MHz), 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 111) t9 t10 t9 t10 t11 t11 Y0 Y1 Y2 Y3 Y4 Y5 ED/HD INPUT SD INPUT S9 TO S2/ S9 TO S0 CLKIN_A Y2 Cb2 Y1 Cr0 Y0 Cb0 Cr4 Cb4 Cr2 Cb2 Cr0 Cb0 Cr2 Y6 Cb6 C9 TO C2/ C9 TO C0 Y9 TO Y2/ Y9 TO Y0 CLKIN_B P_HSYNC, P_VSYNC, CONTROL INPUTS P_BLANK S_HSYNC, S_VSYNC CONTROL INPUTS t12 t12 Cr2 Cr2 Y2 Y1 Cr0 EH/HD INPUT SD INPUT Cb2 Y1 Cr0 S9 TO S2/ S9 TO S0 CLKIN_A Y9 TO Y2/ Y9 TO Y0 CLKIN_B P_HSYNC, P_VSYNC, CONTROL INPUTS P_BLANK S_HSYNC, S_VSYNC CONTROL INPUTS t9 t10 t9 t10 t12 t11 t12 t11 t12 t11 Y0 Cb0 Cb2 Cb0 Y0 Y2 CLKIN_A Y9 TO Y2/ Y9 TO Y0 CONTROL OUTPUTS Y1 Cr0 Y0 Cb0 Cr2 Y2 Cb2 P_HSYNC, P_VSYNC, CONTROL INPUTS P_BLANK t9 t10 t12 t11 t13 t14 |
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