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ADV7341 数据表(PDF) 44 Page - Analog Devices |
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ADV7341 数据表(HTML) 44 Page - Analog Devices |
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44 / 108 page ![]() ADV7340/ADV7341 Data Sheet Rev. C | Page 44 of 108 SR7 to Bit Number1 Reset SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value 0x8B SD Timing Register 1 (applicable in master modes only, that is, Subaddress 0x8A, Bit 0 = 1) SD HSYNC width 0 0 ta =one clock cycle. 0x00 0 1 ta = four clock cycles. 1 0 ta = 16 clock cycles. 1 1 ta = 128 clock cycles. SD HSYNC to VSYNC delay 0 0 tb = 0 clock cycles. 0 1 tb = four clock cycles. 1 0 tb = eight clock cycles. 1 1 tb = 18 clock cycles. SD HSYNC to VSYNC rising edge delay (Mode 1 only) X2 0 tc = tb. X2 1 tc = tb + 32 μs SD VSYNC width (Mode 2 only) 0 0 One clock cycle. 0 1 Four clock cycles. 1 0 16 clock cycles. 1 1 128 clock cycles. SD HSYNC to pixel data adjust 0 0 0 clock cycles. 0 1 One clock cycle 1 0 Two clock cycles. 1 1 Three clock cycles. 0x8C SD FSC Register 03 Subcarrier Frequency Bits[7:0] x x x x x x x x Subcarrier Frequency Bits[7:0]. 0x1F 0x8D SD FSC Register 13 Subcarrier Frequency Bits[15:8] x x x x x x x x Subcarrier Frequency Bits[15:8]. 0x7C 0x8E SD FSC Register 23 Subcarrier Frequency Bits[23:16] x x x x x x x x Subcarrier Frequency Bits[23:16]. 0xF0 0x8F SD FSC Register 33 Subcarrier Frequency Bits[31:24] x x x x x x x x Subcarrier frequency Bits[31:24]. 0x21 0x90 SD FSC phase Subcarrier Phase Bits[9:2] x x x x x x x x Subcarrier Phase Bits[9:2]. 0x00 0x91 SD closed captioning Extended data on even fie lds x x x x x x x x Extended Data Bits[7:0]. 0x00 0x92 SD closed captioning Extended data on even fields x x x x x x x x Extended Data Bits[15:8]. 0x00 0x93 SD closed captioning Data on odd fields x x x x x x x x Data Bits[7:0]. 0x00 0x94 SD closed captioning Data on odd fields x x x x x x x x Data Bits[15:8]. 0x00 0x95 SD Pedestal Register 0 Pedestal on odd fields 17 16 15 14 13 12 11 10 Setting any of these bits to 1 disables the pedestal on the line number indicated by the bit settings. 0x00 0x96 SD Pedestal Register 1 Pedestal on odd fields 25 24 23 22 21 20 19 18 0x00 0x97 SD Pedestal Register 2 Pedestal on even fields 17 16 15 14 13 12 11 10 0x00 0x98 SD Pedestal Register 3 Pedestal on even fields 25 24 23 22 21 20 19 18 0x00 1 x = Logic 0 or Logic 1. 2 X = don’t care. 3 SD subcarrier frequency registers default to NTSC subcarrier frequency values. |
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