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ADV7341 数据表(PDF) 19 Page - Analog Devices |
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ADV7341 数据表(HTML) 19 Page - Analog Devices |
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19 / 108 page  Data Sheet ADV7340/ADV7341 Rev. C | Page 19 of 108 Figure 16. HD-SDR, 16-/20-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Figure 17. HD-DDR, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Y0 Y1 Y2 Y3 b a Cr2 Cb2 Cr0 Cb0 c Y OUTPUT P_HSYNC P_VSYNC P_BLANK Y9 TO Y2/ Y9 TO Y0 C9 TO C2/ C9 TO C0 a AND b AS PER RELEVANT STANDARD. c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Y9 TO Y2/ Y9 TO Y0 Cb0 Y0 Cr0 Y1 b a P_HSYNC P_VSYNC P_BLANK c Y OUTPUT a AND b AS PER RELEVANT STANDARD. c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. |
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