ADV7341_15 datasheet(55/108 Pages) AD

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Data Sheet

ADV7340/ADV7341

Rev. C | Page 55 of 108

ED/HD TIMING RESET

Subaddress 0x34, Bit 0

An ED/HD timing reset is achieved by toggling the ED/HD timing

reset control bit (Subaddress 0x34, Bit 0) from 0 to 1. In this state,

the horizontal and vertical counters remain reset. When this bit

is set back to 0, the internal counters resume counting. This

timing reset applies to the ED/HD timing counters only.

SD SUBCARRIER FREQUENCY LOCK

Subcarrier Frequency Lock (SFL) Mode

In this mode (Subaddress 0x84, Bits[2:1] = 11), the ADV7340/

ADV7341 can be used to lock to an external video source. The

SFL mode allows the ADV7340/ADV7341 to automatically alter

the subcarrier frequency to compensate for line length variations.

When the part is connected to a device such as an ADV7403

video decoder (see Figure 59) that outputs a digital data stream

in the SFL format, the part automatically changes to the com-

pensated subcarrier frequency on a line-by-line basis. This digital

data stream is 67 bits wide, and the subcarrier is contained in

Bit 0 to Bit 21. Each bit is two clock cycles long.

SD VCR FF/RW SYNC

Subaddress 0x82, Bit 5

In DVD record applications where the encoder is used with a

decoder, the VCR FF/RW sync control bit can be used for non-

standard input video, that is, in fast forward or rewind modes.

In fast forward mode, the sync information at the start of a new

field in the incoming video usually occurs before the correct

number of lines/fields is reached. In rewind mode, this sync

signal usually occurs after the total number of lines/fields is

reached. Conventionally, this means that the output video has

corrupted field signals because one signal is generated by the

incoming video and another is generated when the internal

line/field counters reach the end of a field.

When the VCR FF/RW sync control is enabled (Subaddress 0x82,

Bit 5), the line/field counters are updated according to the

incoming VSYNC signal and when the analog output matches

the incoming VSYNC signal. This control is available in all

slave-timing modes except slave Mode 0.

VERTICAL BLANKING INTERVAL

Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4

The ADV7340/ADV7341 are able to accept input data that

contains VBI data (such as CGMS, WSS, VITS) in SD, ED, and

HD modes.

If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD;

Subaddress 0x83, Bit 4 for SD), VBI data is not present at the

output and the entire VBI is blanked. These control bits are

valid in all master and slave timing modes.

For the SMPTE 293M (525p) standard, VBI data can be

inserted on Line 13 to Line 42 of each frame or on Line 6 to

Line 43 for the ITU-R BT.1358 (625p) standard. VBI data can

be present on Line 10 to Line 20 for NTSC and on Line 7 to

Line 22 for PAL.

In SD Timing Mode 0 (slave option), if VBI is enabled, the

blanking bit in the EAV/SAV code is overwritten. It is possible

to use VBI in this timing mode as well.

If CGMS is enabled and VBI is disabled, the CGMS data is,

nevertheless, available at the output.

Figure 59. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits[2:1] = 11)

LLC1

SFL

P[19:10]

ADV7403

VIDEO

DECODER

CLKIN_A

SFL

Y[9:0]/S[9:0]5

RTC

LOW

128

TIME SLOT 01

FSC PLL INCREMENT2

VALID

SAMPLE

INVALID

SAMPLE

6768

RESET BIT4

RESERVED

ADV7340/ADV7341

8/LINE

LOCKED

CLOCK

5 BITS

RESERVED

1FOR EXAMPLE, VCR OR CABLE.

2FSC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7340/ADV7341 FSC DDS REGISTER IS

FSC PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS.

3SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED

NTSC: 0 = NO CHANGE

4RESET ADV7340/ADV7341 DDS.

5SELECTED BY SUBADDRESS 0x01, BIT 7.

COMPOSITE

VIDEO1

H/L TRANSITION

COUNT START

14 BITS

SUBCARRIER

PHASE

SEQUENCE

BIT3

DAC 1

DAC 2

DAC 3

DAC 4

DAC 5

DAC 6

4 BITS

RESERVED

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