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ADV7341 数据表(PDF) 47 Page - Analog Devices |
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ADV7341 数据表(HTML) 47 Page - Analog Devices |
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47 / 108 page  Data Sheet ADV7340/ADV7341 Rev. C | Page 47 of 108 Table 32. Register 0xA6 to Register 0xBB SR7 to Bit Number1 Register Reset SR0 Register Bit Description 7 6 5 4 3 2 1 0 Setting Value 0xA6 SD Gamma A0 SD Gamma Curve A (Point 24) x x x x x x x x A0 0x00 0xA7 SD Gamma A1 SD Gamma Curve A (Point 32) x x x x x x x x A1 0x00 0xA8 SD Gamma A2 SD Gamma Curve A (Point 48) x x x x x x x x A2 0x00 0xA9 SD Gamma A3 SD Gamma Curve A (Point 64) x x x x x x x x A3 0x00 0xAA SD Gamma A4 SD Gamma Curve A (Point 80) x x x x x x x x A4 0x00 0xAB SD Gamma A5 SD Gamma Curve A (Point 96) x x x x x x x x A5 0x00 0xAC SD Gamma A6 SD Gamma Curve A (Point 128) x x x x x x x x A6 0x00 0xAD SD Gamma A7 SD Gamma Curve A (Point 160) x x x x x x x x A7 0x00 0xAE SD Gamma A8 SD Gamma Curve A (Point 192) x x x x x x x x A8 0x00 0xAF SD Gamma A9 SD Gamma Curve A (Point 224) x x x x x x x x A9 0x00 0xB0 SD Gamma B0 SD Gamma Curve B (Point 24) x x x x x x x x B0 0x00 0xB1 SD Gamma B1 SD Gamma Curve B (Point 32) x x x x x x x x B1 0x00 0xB2 SD Gamma B2 SD Gamma Curve B (Point 48) x x x x x x x x B2 0x00 0xB3 SD Gamma B3 SD Gamma Curve B (Point 64) x x x x x x x x B3 0x00 0xB4 SD Gamma B4 SD Gamma Curve B (Point 80) x x x x x x x x B4 0x00 0xB5 SD Gamma B5 SD Gamma Curve B (Point 96) x x x x x x x x B5 0x00 0xB6 SD Gamma B6 SD Gamma Curve B (Point 128) x x x x x x x x B6 0x00 0xB7 SD Gamma B7 SD Gamma Curve B (Point 160) x x x x x x x x B7 0x00 0xB8 SD Gamma B8 SD Gamma Curve B (Point 192) x x x x x x x x B8 0x00 0xB9 SD Gamma B9 SD Gamma Curve B (Point 224) x x x x x x x x B9 0x00 0xBA SD brightness detect SD brightness value x x x x x x x x Read only 0xXX 0xBB Field count Field count x x x Read only 0x0X Reserved 0 0 0 Reserved Encoder version code 0 0 Read only; first encoder version2 0 1 Read only; second encoder version 1 x = Logic 0 or Logic 1. 2 See the HD Interlace External P_HSYNC and P_VSYNC Considerations section for information about the first encoder revision. Table 33. Register 0xBD to Register 0xC8 SR7 to Bit Number1 Reset SR0 Register Bit Description 7 6 5 4 3 2 1 0 Register Setting Value 0xBD SD CSC Matrix 1 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for a1 0x42 0xBE SD CSC Matrix 2 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for a2 0x81 0xBF SD CSC Matrix 3 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for a3 0x19 0xC0 SD CSC Matrix 4 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for a4 0x10 0xC1 SD CSC Matrix 5 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for b1 0x70 0xC2 SD CSC Matrix 6 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for b2 0x5E 0xC3 SD CSC Matrix 7 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for b3 0x12 0xC4 SD CSC Matrix 8 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for b4 0x80 0xC5 SD CSC Matrix 9 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for c1 0x26 0xC6 SD CSC Matrix 10 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for c2 0x4A 0xC7 SD CSC Matrix 11 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for c3 0x70 0xC8 SD CSC Matrix 12 SD CSC matrix coefficient x x x x x x x x Bits[7:0] for c4 0x80 1 x = Logic 0 or Logic 1. |
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