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ADV7341 数据表(PDF) 96 Page - Analog Devices |
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ADV7341 数据表(HTML) 96 Page - Analog Devices |
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96 / 108 page  ADV7340/ADV7341 Data Sheet Rev. C | Page 96 of 108 CONFIGURATION SCRIPTS The scripts listed in the following pages can be used to configure the ADV7340/ ADV7341 for basic operation. Certain features are enabled by default. If required for a specific application, additional features can be enabled. Table 64 lists the scripts available for SD modes of operation. Similarly, Table 85 and Table 112 list the scripts available for ED and HD modes of operation, respectively. For all scripts, only the necessary register writes are included. All other registers are assumed to have their default values. STANDARD DEFINITION Table 64. SD Configuration Scripts Input Format Input Data Width1 Synchronization Format Input Color Space Output Color Space Table Number 525i (NTSC) 10-bit SDR EAV/SAV YCrCb YPrPb and CVBS/Y-C Table 65 525i (NTSC) 10-bit SDR HSYNC/VSYNC YCrCb YPrPb and CVBS/Y-C Table 66 525i (NTSC) 10-bit SDR EAV/SAV YCrCb RGB and CVBS/Y-C Table 67 525i (NTSC) 10-bit SDR HSYNC/VSYNC YCrCb RGB and CVBS/Y-C Table 68 525i (NTSC) 20-bit SDR HSYNC/VSYNC YCrCb YPrPb and CVBS/Y-C Table 69 525i (NTSC) 20-bit SDR HSYNC/VSYNC YCrCb RGB and CVBS/Y-C Table 70 525i (NTSC) 30-bit SDR HSYNC/VSYNC RGB YPrPb and CVBS/Y-C Table 71 525i (NTSC) 30-bit SDR HSYNC/VSYNC RGB RGB and CVBS/Y-C Table 72 NTSC Sq. Pixel 10-bit SDR EAV/SAV YCrCb CVBS/Y-C (S-Video) Table 73 NTSC Sq. Pixel 30-bit SDR HSYNC/VSYNC RGB CVBS/Y-C (S-Video) Table 74 625i (PAL) 10-bit SDR EAV/SAV YCrCb YPrPb and CVBS/Y-C Table 75 625i (PAL) 10-bit SDR HSYNC/VSYNC YCrCb YPrPb and CVBS/Y-C Table 76 625i (PAL) 10-bit SDR EAV/SAV YCrCb RGB and CVBS/Y-C Table 77 625i (PAL) 10-bit SDR HSYNC/VSYNC YCrCb RGB and CVBS/Y-C Table 78 625i (PAL) 20-bit SDR HSYNC/VSYNC YCrCb YPrPb and CVBS/Y-C Table 79 625i (PAL) 20-bit SDR HSYNC/VSYNC YCrCb RGB and CVBS/Y-C Table 80 625i (PAL) 30-bit SDR HSYNC/VSYNC RGB YPrPb and CVBS/Y-C Table 81 625i (PAL) 30-bit SDR HSYNC/VSYNC RGB RGB and CVBS/Y-C Table 82 PAL Sq. Pixel 10-bit SDR EAV/SAV YCrCb CVBS/Y-C (S-Video) Table 83 PAL Sq. Pixel 30-bit SDR HSYNC/VSYNC RGB CVBS/Y-C (S-Video) Table 84 1 SDR = single data rate. Table 65. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb and CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0xFC All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC9 Pixel data valid. YPrPb and CVBS/Y-C out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 0x88 0x10 10-bit input enabled. Table 66. 10-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0xFC All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. 0x82 0xC9 Pixel data valid. YPrPb and CVBS/Y-C out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. 0x88 0x10 10-bit input enabled. 0x8A 0x0C Timing Mode 2 (slave). HSYNC/VSYNC synchronization. |
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