ADV7341_15 datasheet(23/108 Pages) AD

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Data Sheet

ADV7340/ADV7341

Rev. C | Page 23 of 108

Pin No.

Mnemonic

Input/

Output

Description

45, 35

COMP1,

COMP2

Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to VAA.

44, 43, 42

DAC 1, DAC 2,

DAC 3

DAC Outputs. Full- and low-drive capable DACs.

39, 38, 37

DAC 4, DAC 5,

DAC 6

DAC Outputs. Low-drive only capable DACs.

SCL

I2C Clock Input.

SDA

I/O

I2C Data Input/Output.

ALSB

This signal sets up the LSB2 of the MPU I2C address (see the Power Supply Sequencing section for

more information).

VREF

Optional External Voltage Reference Input for DACs or Voltage Reference Output.

VAA

Analog Power Supply (3.3 V).

10, 56

VDD

Digital Power Supply (1.8 V). For dual-supply configurations, VDD can be connected to other 1.8 V

supplies through a ferrite bead or suitable filtering.

VDD_IO

Input/Output Digital Power Supply (1.8 V or 3.3 V).

PVDD

PLL Power Supply (1.8 V). For dual-supply configurations, PVDD can be connected to other 1.8 V

supplies through a ferrite bead or suitable filtering.

EXT_LF1

External Loop Filter for On-Chip PLL 1.

EXT_LF2

External Loop Filter for On-Chip PLL 2.

PGND

PLL Ground Pin.

AGND

Analog Ground Pin.

11, 57

DGND

Digital Ground Pin.

GND_IO

Input/Output Supply Ground Pin.

ED = enhanced definition = 525p and 625p.

LSB = least significant bit. In the ADV7340, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6.

In the ADV7341, setting the LSB to 0 sets the I2C address to 0x54. Setting it to 1 sets the I2C address to 0x56.

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