ADV7341_15 datasheet(70/108 Pages) AD

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ADV7340/ADV7341

Data Sheet

Rev. C | Page 70 of 108

Table 57. VSYNC Output Control1, 2

ED/HD Input

Sync Format

(Subaddress

0x30, Bit 2)

ED/HD VSYNC

Control

(Subaddress

0x34, Bit 2)

ED/HD Sync

Output

Enable

(Subaddress

0x02, Bit 7)

SD Sync Output

Enable (Subad-

dress 0x02, Bit 6)

Video Standard

Signal on S_VSYNC Pin

Duration

Three-state

N/A

Interlaced

Pipelined SD VSYNC/Field

See SD Timing

Pipelined ED/HD VSYNC

or field signal

As per VSYNC or

field signal timing

All HD interlaced

standards

Pipelined field signal

based on the AV Code F bit

Field

All ED/HD progressive

standards

Pipelined VSYNC based

on the AV Code V bit

Vertical blanking

interval

All ED/HD standards

except 525p

Pipelined ED/HD VSYNC

based on the vertical

counter

Aligned with

serration lines

525p

Pipelined ED/HD VSYNC

based on the vertical

counter

Vertical blanking

interval

In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.

X = don’t care.

LOW POWER MODE

Subaddress 0x0D, Bits[2:0]

For power-sensitive applications, the ADV7340/ADV7341

support an Analog Devices proprietary low power mode of

operation on DAC 1, DAC 2, and DAC 3. To use this low power

mode, these DACs must be operating in full-drive mode (RSET1 =

510 Ω, RL = 37.5 Ω). Low power mode is not available in low-

drive mode (RSET = 4.12 kΩ, RL = 300 Ω). Low power mode can

be independently enabled or disabled on DAC 1, DAC 2, and

DAC 3 using Subaddress 0x0D, Bits[2:0]. Low power mode is

disabled by default on each DAC.

In low power mode, DAC current consumption is content

dependent. On a typical video stream, it can be reduced by as

much as 40%. For applications requiring the highest possible video

performance, low power mode should be disabled.

CABLE DETECTION

Subaddress 0x10

The ADV7340/ADV7341 include an Analog Devices proprietary

cable detection feature. The cable detection feature is available

on DAC 1 and DAC 2, while operating in full-drive mode (RSET1

= 510 Ω, RL1 = 37.5 Ω, assuming a connected cable). The feature

is not available in low-drive mode (RSET1 = 4.12 kΩ, RL = 300 Ω).

For a DAC to be monitored, the DAC must be powered up in

Subaddress 0x00.

The cable detection feature can be used with all SD, ED, and

HD video standards. It is available for all output configurations,

that is, CVBS, YC, YPrPb, and RGB output configurations.

For CVBS/YC output configurations, both DAC 1 and DAC 2

are monitored; that is, the CVBS and YC luma outputs are

monitored. For YPrPb and RGB output configurations, only

DAC 1 is monitored; that is, the luma or green output is

monitored.

Once per frame, the ADV7340/ADV7341 monitor DAC 1

and/or DAC 2, updating Subaddress 0x10, Bit 0 and Bit 1,

respectively. If a cable is detected on one of the DACs, the

relevant bit is set to 0. If not, the bit is set to 1.

DAC AUTOPOWER-DOWN

Subaddress 0x10, Bit 4

For power-sensitive applications, a DAC autopower-down feature

can be enabled using Subaddress 0x10, Bit 4. This feature is

available only when the cable detection feature is enabled.

With this feature enabled, the cable detection circuitry monitors

DAC 1 and/or DAC 2 once per frame. If they are unconnected,

some or all of the DACs automatically power down. Which

DAC or DACs are powered down depends on the selected

output configuration.

For CVBS/YC output configurations, if DAC 1 is unconnected,

only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and

DAC 3 power down.

For YPrPb and RGB output configurations, if DAC 1 is uncon-

nected, all three DACs power down. DAC 2 is not monitored

for YPrPb and RGB output configurations.

Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is

detected, the appropriate DAC or DACs remain powered up for

the duration of the frame. If no cable is detected, the appropriate

DAC or DACs power down until the next frame when the

process is repeated.

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