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ADV7341 数据表(PDF) 52 Page - Analog Devices |
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ADV7341 数据表(HTML) 52 Page - Analog Devices |
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52 / 108 page  ADV7340/ADV7341 Data Sheet Rev. C | Page 52 of 108 The ED/HD-DDR 8-/10-bit 4:2:2 CrCb pixel data is also input on Pin Y9 to Pin Y2/Y0 on the opposite edge of CLKIN_B. Pin Y0 is the LSB in 10-bit input mode. Whether the ED/HD Y data is clocked in on the rising or falling edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1] (see the input sequence shown in Figure 52 and Figure 53). Figure 55. Simultaneous SD and ED Example Application Figure 56. Simultaneous SD and HD Example Application ENHANCED DEFINITION ONLY (AT 54 MHz) Subaddress 0x01, Bits[6:4] = 111 Enhanced definition (ED) YCrCb data can be input in an interleaved 4:2:2 format on an 8-/10-bit bus at a rate of 54 MHz. A 54 MHz clock signal must be provided on the CLKIN_A pin. Input synchronization signals are provided on the P_HSYNC, P_VSYNC, and P_BLANK pins. The interleaved pixel data is input on Pin Y9 to Pin Y2/Y0, with Pin Y0 being the LSB in 10-bit input mode. Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV) Figure 58. ED Only (at 54 MHz) Example Application CLKIN_A CLKIN_B S[9:0] C[9:0] Y[9:0] ED DECODER S_VSYNC, S_HSYNC P_VSYNC, P_HSYNC, P_BLANK 27MHz 10 CrCb 10 Y 3 2 YCrCb 27MHz 10 SD DECODER 525p OR 625p ADV7340/ ADV7341 CLKIN_A CLKIN_B S[9:0] C[9:0] Y[9:0] HD DECODER S_VSYNC, S_HSYNC P_VSYNC, P_HSYNC, P_BLANK 74.25MHz 10 CrCb 10 Y 3 2 YCrCb 27MHz 10 SD DECODER 1080i OR 720p OR 1035i ADV7340/ ADV7341 3FF 00 00 XY Cb0 Y0 Y1 Cr0 CLKIN_A Y9–Y0 MPEG2 DECO DER CLKIN_A Y[9:0] 54MHz P_VSYNC, P_HSYNC, P_BLANK YCrCb 10 YCrCb 3 INTERLACED TO PROGRESSIVE ADV7340/ ADV7341 |
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