ADV7341_15 datasheet(82/108 Pages) AD

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ADV7340/ADV7341

Data Sheet

Rev. C | Page 82 of 108

INTERNAL TEST PATTERN GENERATION

SD TEST PATTERNS

The ADV7340/ADV7341 are able to internally generate SD

color bar and black bar test patterns. For this function, a 27 MHz

clock signal must be applied to the CLKIN_A pin.

The register settings in Table 61 are used to generate an SD

NTSC 75% color bar test pattern. CVBS output is available on

DAC 4, S-Video (Y-C) output is on DAC 5 and DAC 6, and

YPrPb output is on DAC 1 to DAC 3. On power-up, the

subcarrier frequency registers default to the appropriate values

for NTSC. All other registers are set as normal/default.

Table 61. SD NTSC Color Bar Test Pattern Register Writes

Subaddress

Setting

0x00

0xFC

0x82

0xC9

0x84

0x40

To generate an SD NTSC black bar test pattern, the settings

shown in Table 61 should be used with an additional write of

0x24 to Subaddress 0x02.

For PAL output of either test pattern, the same settings are used,

except that Subaddress 0x80 is programmed to 0x11, and the

subcarrier frequency registers are programmed as shown in

Table 62.

Table 62. PAL FSC Register Writes

Subaddress

Description

Setting

0x8C

FSC0

0xCB

0x8D

FSC1

0x8A

0x8E

FSC2

0x09

0x8F

FSC3

0x2A

Note that, when programming the FSC registers, the user must

write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full

FSC value to be written is accepted only after the FSC3 write is

complete.

ED/HD TEST PATTERNS

The ADV7340/ADV7341 are able to internally generate an

ED/HD black bar and hatch test patterns. For ED test patterns, a

27 MHz clock signal must be applied to the CLKIN_A pin. For

HD test patterns, a 74.25 MHz clock signal must be applied to

the CLKIN_A pin.

The register settings in Table 63 are used to generate an ED

525p hatch test pattern. YPrPb output is available on DAC 1 to

DAC 3. All other registers are set as normal/default.

Table 63. ED 525p Hatch Test Pattern Register Writes

Subaddress

Setting

0x00

0x1C

0x01

0x10

0x31

0x05

To generate an ED 525p black bar test pattern, the settings

shown in Table 63 should be used with an additional write of

0x24 to Subaddress 0x02.

To generate an ED 525p flat field test pattern, the settings

shown in Table 63 should be used, except that 0x0D should be

written to Subaddress 0x31.

The Y, Cr, and Cb levels for the hatch and flat field test patterns

can be controlled using Subaddress 0x36, Subaddress 0x37, and

Subaddress 0x38, respectively.

For ED/HD standards other than 525p, the settings shown in

Table 63 (and subsequent comments) are used, except that

Subaddress 0x30, Bits[7:3] are updated as appropriate.

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