ADV7341_15 datasheet(69/108 Pages) AD

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Data Sheet

ADV7340/ADV7341

Rev. C | Page 69 of 108

EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL

For synchronization purposes, the ADV7340/ADV7341 are able to accept either time codes embedded in the input pixel data or external

synchronization signals provided on the S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC, and P_BLANK pins (see Table 54). It is also

possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 55 to Table 57).

Table 54. Timing Synchronization Signal Input Options

Signal

Condition

SD HSYNC In

S_HSYNC

SD slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0]).1

SD VSYNC In

S_VSYNC

SD Slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0]).1

ED/HD HSYNC In

P_HSYNC

ED/HD timing sync; inputs enabled (Subaddress 0x30, Bit 2 = 0).

ED/HD VSYNC In

P_VSYNC

ED/HD timing sync; inputs enabled (Subaddress 0x30, Bit 2 = 0).

ED/HD BLANK In

P_BLANK

SD and ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02[7:6] = 00).

Table 55. Timing Synchronization Signal Output Options

Signal

Condition

SD HSYNC Out

S_HSYNC

SD timing sync; outputs enabled (Subaddress 0x02, Bit 6 = 1).1

SD VSYNC Out

S_VSYNC

SD timing sync; outputs enabled (Subaddress 0x02, Bit 6 = 1).1

ED/HD HSYNC Out

S_HSYNC

ED/HD timing sync; outputs enabled (Subaddress 0x02, Bit 7 = 1).

ED/HD VSYNC Out

S_VSYNC

ED/HD timing sync; outputs enabled (Subaddress 0x02, Bit 7 = 1).

ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).

Table 56. HSYNC Output Control1, 2

ED/HD Input Sync

Format (Subaddress

0x30, Bit 2)

ED/HD HSYNC

Control

(Subaddress

0x34, Bit 1)

ED/HD Sync

Output Enable

(Subaddress

0x02, Bit 7)

SD Sync Output

Enable

(Subaddress

0x02, Bit 6)

Signal on S_HSYNC Pin

Duration

Three-state.

N/A.

Pipelined SD HSYNC.

See the

SD Timing

section.

Pipelined ED/HD HSYNC.

As per HSYNC timing.

Pipelined ED/HD HSYNC based on

the AV Code H bit.

Same as line blanking

interval.

Pipelined ED/HD HSYNC based on

the horizontal counter.

Same as embedded

HSYNC.

In all ED/HD standards where there is an HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.

X = don’t care.

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